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AD74322DAR Fiches technique(PDF) 8 Page - Analog Devices |
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AD74322DAR Fiches technique(HTML) 8 Page - Analog Devices |
8 / 20 page AD74322 –8– Pr D 03/00 PRELIMINARY TECHNICAL DATA PRELIMINAR Y TECHNICAL DA TA FUNCTIONAL DESCRIPTION ADCSection TherearetwoADCchannelsintheAD74322,configuredasastereo pair.EachADCchannelcanbeindependentlymuted. Theinputpins areswitchedbetweendifferentialinputsorfoursingleendedinputs accordingly. Thegainblockcanbeprogrammedforindependentleftand rightgains,instepsof+3dB,from0dBto+12dB. TheADCoperatesat anoversamplingratioof128andthedecimationfilterreducestheoutput to the standard sample rates. The output maximum sample rate is 96 kHz at ASDATA. AutomaticLevelControl AnalogSigmaDeltaModulator DecimatorSection Thedigitaldecimationfilterhasapassbandrippleof ±0.01dBanda stopbandattenuationof70dB. ThefilterisanFIRtypewithalinear phaseresponse. Thegroupdelayat48kHzis ??us. Outputsamplerates up to 96 kHz are supported. InputSignalswing Each ADC input has an input range of 0.5 VRMS / 1.414 VP-P (Single- Ended) about a bias point equal to VREFCAP(SeeFigure <Input_Swing>) AD743xx VINPx VINNx VREFCAP 1.414 V P-P VREFCAP 1.414 V P-P Figure <Input_Swing> DACSection TheAD74322hastwoDACchannelsarrangedasastereopair,withtwo, fullydifferentialvoltage,analogoutputsforimprovednoiseanddistortion performance. Eachchannelhasit’sownindependentlyprogrammable attenuatorwithamaximumattenuationof63dB,adjustablein1dBsteps. Digitalinputsareviaaserialdatainputpinandacommonframe (DLRCLK)andbit(DBLCK)clockorusinga‘packeddata’mode,both channelscanbeinputusingasingledatapin. InterpolatorSection DigitalSigmaDeltaModulator DAC AnalogOutputFilter OutputSignalswing Each ADC input has an output range of 0.5 VRMS / 1.414 VP-P (Single- Ended) about a bias point equal to VREFCAP(SeeFigure <Output_Swing>) AD743xx VOUTPx VOUTNx VREFCAP 1.414 V P-P VREFCAP 1.414 V P-P Figure <Output_Swing> Reference The AD74322 features an on-chip reference whose nominal value is 1.125 V.A __ nF capacitor applied at the REFCAP pin is necessary to stabilise the referrence. (See Figure <REFCAP_Int>) AD743xx REFCAP Figure <REFCAP_Int> If it is required to use an external reference, because of its value or its referencetempco,theinternalreferencecanbedisabledviaControl Register__andtheexternalreferenceappliedattheREFCAPpin(See Figure<REFCAP_Ext>). EXTERNAL REFERENCE AD743xx REFCAP 1.0 V Figure <REFCAP_Ext> MasterClockingScheme TheupdaterateoftheAD74322’sADCandDACchannelsrequirean internalmasterclock(IMCLK)whichis256timesthatsampleupdate rate(IMCLK=256*FS).Inordertoprovidesomeflexibilityin selecting sample rates, the device has a series of three master clock pre-scalers which are programmable and allow the user to choose a range of convenient sample rates from a single external master clock. The master clock signal to the AD74322 is applied at the MCLK pin. The MCLK signal is passed through a series of two programmable MCLK pre-scalers (divider) circuits which can be selected to reduce the resulting Internal MCLK (IMCLK) frequency if required. The first MCLK pre- scaler provides divider ratios of /1 (pass through), /2, /3 while the second pre-scaler provides divider ratios of ./1 (pass through), /2, /4 and the third pre-scaler provides ratios of /1 (pass through), /2 and /5.. MCLK IMCLK Programmable MCLK Divider Control Reg /1 /2 /3 /1 /2 /4 Pre-Scaler 1 Pre-Scaler 2 |
Numéro de pièce similaire - AD74322DAR |
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Description similaire - AD74322DAR |
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