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AD676JD Fiches technique(PDF) 6 Page - Analog Devices

No de pièce AD676JD
Description  16-Bit 100 kSPS Sampling ADC
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD676JD Fiches technique(HTML) 6 Page - Analog Devices

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AD676
REV. A
–6–
PIN DESCRIPTION
Pin
Name
Type
Description
1–6
BIT 11-BIT 16
DO
BIT 11–BIT 16 represent the six LSBs of data.
7
BUSY
DO
Status Line for Converter. Active HIGH, indicating a conversion or calibration in progress.
BUSY should be buffered when capacitively loaded.
8
CAL
DI
Calibration Control Pin (Asynchronous).
9
SAMPLE
DI
VIN Acquisition Control Pin. Active HIGH. During conversion, SAMPLE controls the state
of the internal sample-hold amplifier and the falling edge initiates conversion (see “Conver-
sion Control” paragraph). During calibration, SAMPLE should be held LOW. If HIGH dur-
ing calibration, diagnostic information will appear on the two LSBs (Pins 5 and 6).
10
CLK
DI
Master Clock Input. The AD676 requires 17 clock cycles to execute a conversion.
11
DGND
P
Digital Ground.
12
VCC
P
+12 V Analog Supply Voltage.
13
AGND
P/AI
Analog Ground.
14
AGND SENSE
AI
Analog Ground Sense.
15
VIN
AI
Analog Input Voltage.
16
VREF
AI
External Voltage Reference Input.
17
VEE
P
–12 V Analog Supply Voltage. Note: the lid of the ceramic package is internally connected to
VEE.
18
VDD
P
+5 V Logic Supply Voltage.
19–28
BIT 1–BIT 10
DO
BIT 1–BIT 10 represent the ten MSB of data.
Type: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TOP VIEW
(Not to Scale)
AD676
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
VDD
V
EE
V
REF
VIN
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
BIT 16 (LSB)
BUSY
CAL
SAMPLE
CLK
DGND
VCC
AGND
AGND SENSE
Package Pinout
DIGITAL
CHIP
PAT
GEN
ALU
RAM
MICRO-CODED
CONTROLLER
AGND
AGND SENSE
CAL
SAMPLE
BUSY
COMP
ANALOG
CHIP
16-BIT
DAC
INPUT
BUFFERS
LOGIC & TIMING
CAL
DAC
LEVEL TRANSLATORS
16
BIT 1 – BIT 16
V
IN
VREF
15
14
16
13
8
9
AD676
SAR
1
6
19
28
CLK 10
L
A
T
C
H
7
Functional Block Diagram


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