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AD569AD Fiches technique(PDF) 3 Page - Analog Devices |
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AD569AD Fiches technique(HTML) 3 Page - Analog Devices |
3 / 12 page AD569 REV. A –3– AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance Only and are not subject to test. +VS = +12 V; –VS = –12 V; +VREF = +5 V; –VREF = –5 V excepts where stated. Parameter Limit Units Test Conditions/Comments Output Voltage Settling 5 µs max No Load Applied (Time to ±0.001% FS 3 µs typ (DAC output measured from falling edge of LDAC.) For FS Step) 6 µs max VOUT Load = 1 kΩ, CLOAD = 1000 pF. 4 µs typ (DAC output measured from falling edge of LDAC. ) Digital-to-Analog Glitch 500 nV-sec typ Measured with VREF = 0 V. DAC registers alternatively loaded Impulse with input codes of 8000H and 0FFFH (worst-case transition). Load = 1 k Ω. Multiplying Feedthrough –100 dB max +VREF = 1 V rms 10 kHz sine wave, –VREF = 0 V Output Noise Voltage 40 nV/ Hz typ Measured between VOUT and –VREF Density (1 kHz-1 MHz) TIMING CHARACTERISTICS (+VS = +12 V, –VS = –12 V, VIH = 2.4 V, VIL = 0.4 V,TMIN to TMAX) Parameter Limit Units Test Conditions/Comments Case A 150 ns Pulse on HBE, LBE, and LDAC THS = 140 ns min, THH = 10 ns min tWC 120 ns min CS Pulse Width tSC 60 ns min CS Data Setup Time tHC 20 ns min CS Data Hold Time Case B None tWB 70 ns min HBE , LBE Pulse Width tSB 80 ns min HBE , LBE Data Setup Time tHB 20 ns min HBE , LBE Data Hold Time tSCS 120 ns min CS Setup Time tHCS 10 ns min CS Hold Time tWD 120 ns min LDAC Pulse Width Case C None tWB 120 ns min HBE , LBE Pulse Width tSB 80 ns min HBE , LBE Data Setup Time tHB 20 ns min HBE , LBE Data Hold Time tSCS 120 ns min CS Setup Time tHCS 10 ns min CS Hold Time Figure 2a. AD569 Timing Diagram – Case B Figure 2b. AD569 Timing Diagram – Case C Figure 1. AD569 Timing Diagram – Case A |
Numéro de pièce similaire - AD569AD |
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Description similaire - AD569AD |
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