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TPS92510DGQR Fiches technique(PDF) 11 Page - Texas Instruments |
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TPS92510DGQR Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 28 page ( ) ( ) DELAY 0.7 V R1 32 A t C1 32 A - ´ m = ´ m TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 OVERVIEW The TPS92510 is a 60-V, 1.5-A, step-down (buck) regulator with an integrated high-side N-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, peak-current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. The TPS92510 has a default start up voltage of approximately 2.5 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device operates. The operating current is 138 μA when not switching and under no load. When the device is disabled, the supply current is 1.3 μA. The integrated 200 m Ω high-side MOSFET allows for high efficiency power supply designs capable of delivering 1.5 A of continuous current to a load. The TPS92510 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS92510 can operate at high duty cycles because of the boot UVLO. DETAILED DESCRIPTION Start-Up The VIN and EN UVLO conditions must be satisfied before the TPS92510 is allowed to switch. When the EN pin is held low the device enters a low-power shutdown mode, and some internal circuits are deactivated to conserve power. When EN returns high these circuits are enabled, which results in a delay of approximately 50 µs (typical) before switching starts. During start-up the TPS92510 operates in a minimum pulse width mode, which is an open-loop control. At the start of each switching cycle the internal oscillator initiates a SET pulse. The high-side MOSFET turns on with a minimum pulse width of 300 ns (typical), independent of the COMP voltage. The device does not pulse skip. While operating in minimum pulse width mode the LED bypass capacitor is being charged, causing an in-rush current. Also, the COMP voltage begins to rise as the error amplifier output current charges the compensation network. When the COMP voltage reaches approximately 0.7 V, the error amplifier is ensured to be out of saturation and to have sufficient gain to regulate the loop. The TPS92510 then transitions from minimum pulse width mode to regulation mode. During regulation mode the error amplifier is now in closed-loop control of the system. The gain of the error amplifier quickly increases the duty cycle, which causes the output voltage to increase. Once the output voltage approaches the forward voltage of the LED string the LED current quickly begins to increase until it reaches regulation. There is a slight delay from the time the VIN and EN UVLO conditions are satisfied until the time the error amplifier has control of the feedback loop. This delay is a result of the time it takes COMP to charge the compensation components to 0.7 V. This delay can be approximated as shown in Equation 1 . where • C1 is the integrator capacitor from COMP to GND • R1 is the resistor in series with the integrator capacitor (1) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS92510 |
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