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AD1958YRSRL Fiches technique(PDF) 5 Page - Analog Devices |
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AD1958YRSRL Fiches technique(HTML) 5 Page - Analog Devices |
5 / 8 page REV. 0 AD1958 –5– PIN FUNCTION DESCRIPTIONS Pin Input/Output Mnemonic Description 1 I CCLK Control Clock Input for Control Data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. 2I CLATCH Latch Input for Control Data 3I RESET Reset. The AD1958 is placed in a reset mode when this pin is held LO. The serial control port registers are reset to their default values. Set HI for normal operation. 4 I LRCLK Left/Right Clock Input for Input Data. Must run continuously. 5 I BCLK Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a burst fashion. 6 I SDATA Serial input, MSB first, containing two channels of 16/20/24 bits of two’s- complement data per channel. 7 I DVDD Digital Power Supply Connect to Digital 5 V Supply 8 I DGND Digital Ground 9 O SCLK0 33.8688 MHz Clock Output 10 O SCLK1 256/384/512/768 fS Output 11 O SCLK2 16.9344 MHz/22.5792 MHz/512 fS Output 12 I/O MCLK 27 MHz Master Clock Output/256 fS DAC Clock Input 13 O XOUT 27 MHz Crystal Oscillator Output 14 I XIN 27 MHz Crystal Oscillator/External Clock Input 15 PVDD PLL Power Supply. Connect to PLL 5 V Supply. 16 PGND PLL Ground 17 LF0 PLL0 Loop Filter 18 LF1 PLL1 Loop Filter 19 AGND0 Analog Ground 20 O OUTR Right Channel Positive Line Level Analog Output 21 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 µF and 0.1 µF capacitors to AGND. 22 I AGND1 Analog Ground 23 O OUTL Left Channel Line Level Analog Output 24 AVDD Analog Power Supply. Connect to Analog 5 V Supply. 25 FILTB Filter Capacitor Connection. Connect 10 µF Capacitor to AGND. 26 O ZERO Zero Flag Output. This pin goes HI when both channels have zero signal input for more than 1024 L/R Clock Cycles. 27 I MUTE Mute. Assert HI to Mute Both Stereo Analog Outputs. Deassert LO for normal operation. 28 I CDATA Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used for specifying channel-specific attenuation and mute. FUNCTIONAL DESCRIPTION DAC The AD1958 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 16384 linear steps. Digital inputs are supplied through a serial data input pin, SDATA, a frame clock, LRCLK, and a bit clock, BLCK. Each analog output pin sits at a dc level of VREF (present at FILTR), and swings ± 1.585 V for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recom- mended to remove high-frequency noise present on the output pins. The output phase can be changed in an SPI control register to accommodate inverting and noninverting filters. Note that the use of op amps with low slew rate or low band- width may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTB and FILTR pins should be bypassed by external capacitors to ground. The FILTB pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin, FILTR (VREF ~ 2.39 V) can be used to bias external op amps used to filter the output signals. The DAC master clock frequency is 256 fS for the 32 kHz–48 kHz range (8 interpolation, see Table I). For the 96 kHz range (4 interpolation) this is 128 fS. At 192 kHz (2 interpolation), this is 64 fS. It is supplied internally from the PLL clock system when MCLK mode is set to Output in the PLL Control Register. When the MCLK mode is changed to Input, it must be supplied from an external source connected to MCLK. The output from the 27 MHz PLL clock is disabled in this case. |
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