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AD5142ABRUZ100-RL7 Fiches technique(PDF) 9 Page - Analog Devices

No de pièce AD5142ABRUZ100-RL7
Description  The AD5122A/AD5142A are available in a compact, 16-lead, 3 mm 횞 3 mm LFCSP and a 16-lead TSSOP.
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5142ABRUZ100-RL7 Fiches technique(HTML) 9 Page - Analog Devices

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Data Sheet
AD5122A/AD5142A
Rev. A | Page 9 of 32
INTERFACE TIMING SPECIFICATIONS
VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
Test Conditions/Comments
Min
Typ
Max
Unit
Description
fSCL2
Standard mode
100
kHz
Serial clock frequency
Fast mode
400
kHz
t1
Standard mode
4.0
µs
SCL high time, tHIGH
Fast mode
0.6
µs
t2
Standard mode
4.7
µs
SCL low time, tLOW
Fast mode
1.3
µs
t3
Standard mode
250
ns
Data setup time, tSU; DAT
Fast mode
100
ns
t4
Standard mode
0
3.45
µs
Data hold time, tHD; DAT
Fast mode
0
0.9
µs
t5
Standard mode
4.7
µs
Setup time for a repeated start condition, tSU; STA
Fast mode
0.6
µs
t6
Standard mode
4
µs
Hold time (repeated) for a start condition, tHD; STA
Fast mode
0.6
µs
t7
Standard mode
4.7
µs
Bus free time between a stop and a start condition, tBUF
Fast mode
1.3
µs
t8
Standard mode
4
µs
Setup time for a stop condition, tSU; STO
Fast mode
0.6
µs
t9
Standard mode
1000
ns
Rise time of SDA signal, tRDA
Fast mode
20 + 0.1 CL
300
ns
t10
Standard mode
300
ns
Fall time of SDA signal, tFDA
Fast mode
20 + 0.1 CL
300
ns
t11
Standard mode
1000
ns
Rise time of SCL signal, tRCL
Fast mode
20 + 0.1 CL
300
ns
t11A
Standard mode
1000
ns
Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 3)
Fast mode
20 + 0.1 CL
300
ns
t12
Standard mode
300
ns
Fall time of SCL signal, tFCL
Fast mode
20 + 0.1 CL
300
ns
tSP3
Fast mode
0
50
ns
Pulse width of suppressed spike (not shown in Figure 3)
t
RESET
0.1
10
µs
RESET low time (not shown in Figure 3)
tEEPROM_PROGRAM4
15
50
ms
Memory program time (not shown in Figure 3)
tEEPROM_READBACK
7
30
µs
Memory readback time (not shown in Figure 3)
tPOWER_UP5
75
µs
Power-on EEPROM restore time (not shown in Figure 3)
tRESET
30
µs
Reset EEPROM restore time (not shown in Figure 3)
1
Maximum bus capacitance is limited to 400 pF.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4
The EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
5
Maximum time after VDD − VSS is equal to 2.3 V.


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