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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD1881AJST Fiches technique(PDF) 5 Page - Analog Devices |
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AD1881AJST Fiches technique(HTML) 5 Page - Analog Devices |
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5 / 26 page  AD1881A –5– REV. 0 TIMING PARAMETERS 1 (GUARANTEED OVER OPERATING TEMPERATURE RANGE) Parameter Symbol Min Typ Max Unit RESET Active Low Pulsewidth tRST_LOW 50 ns RESET Inactive to BIT_CLK Startup Delay tRST2CLK 833 µs SYNC Active High Pulsewidth tSYNC_HIGH 80 ns SYNC Low Pulsewidth tSYNC_LOW 19.5 µs SYNC Inactive to BIT_CLK Startup Delay tSYNC2CLK 162.8 ns BIT_CLK Frequency 12.288 MHz BIT_CLK Period tCLK_PERIOD 81.4 ns BIT_CLK Output Jitter 2 750 ps BIT_CLK High Pulsewidth tCLK_HIGH 36.62 40.69 44.76 ns BIT_CLK Low Pulsewidth tCLK_LOW 36.62 40.69 44.76 ns SYNC Frequency 48.0 kHz SYNC Period tSYNC_PERIOD 20.8 µs Setup to Falling Edge of BIT_CLK tSETUP 5 2.5 ns Hold from Falling Edge of BIT_CLK tHOLD 5ns BIT_CLK Rise Time tRISECLK 24 10 ns BIT_CLK Fall Time tFALLCLK 24 10 ns SYNC Rise Time tRISESYNC 24 10 ns SYNC Fall Time tFALLSYNC 24 10 ns SDATA_IN Rise Time tRISEDIN 24 10 ns SDATA_IN Fall Time tFALLDIN 24 10 ns SDATA_OUT Rise Time tRISEDOUT 24 10 ns SDATA_OUT Fall Time tFALLDOUT 24 10 ns End of Slot 2 to BIT_CLK, SDATA_IN Low tS2_PDOWN 010 ms Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) tSETUP2RST 15 ns Rising Edge of RESET to HI-Z Delay (ATE Test Mode) tOFF 25 ns Propagation Delay 15 ns RESET Rise Time 50 ns NOTES 1Guaranteed, not tested. 2Output jitter is directly dependent on crystal input jitter. Specifications subject to change without notice. |
Numéro de pièce similaire - AD1881AJST |
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Description similaire - AD1881AJST |
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