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AD1864 Datasheet(Fiches technique) 5 Page - Analog Devices

Numéro de pièce AD1864
Description  Complete Dual 18-Bit Audio DAC
Télécharger  12 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD1864 Datasheet(HTML) 5 Page - Analog Devices

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AD1864
?5?
REV. A
TOTAL HARMONIC DISTORTION + NOISE
Total Harmonic Distortion plus Noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the
amplitudes of the harmonics and noise to the value of the
fundamental input frequency. It is usually expressed in percent.
THD+N is a measure of the magnitude and distribution of
linearity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depending
on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small (?20 dB, ?60 dB) signal amplitudes. THD+N measure-
ments for the AD1864 are made using the first 19 harmonics
and noise out to 30 kHz.
SIGNAL-TO-NOISE RATIO
The Signal-to-Noise Ratio is defined as the ratio of the ampli-
tude of the output when a full- scale code is entered to the
amplitude of the output when a midscale code is entered. It is
measured using a standard A-Weight filter. SNR for the
AD1864 is measured for noise components up to 30 kHz.
CHANNEL SEPARATION
Channel separation is defined as the ratio of the amplitude of a
full-scale signal appearing on one channel to the amplitude of
that same signal which couples onto the adjacent channel. It is
usually expressed in dB. For the AD1864 channel separation is
measured in accordance with EIAJ Standard CP-307, Section 5.5.
D-RANGE DISTORTION
D-Range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
60 dB below full-scale is reproduced. D-Range is tested with a
1 kHz input sine wave. This is measured with a standard
A-Weight filter as specified by EIAJ Standard CP-307.
GAIN ERROR
The gain error specification indicates how closely the output of
a given channel matches the ideal output for given input data. It
is expressed in % of FSR and is measured with a full-scale output
signal.
INTERCHANNEL GAIN MATCHING
The gain matching specification indicates how closely the
amplitudes of the output signals match when producing
identical input data. It is expressed in % of FSR (Full-Scale
Range = 6 V for the AD1864) and is measured with full-scale
output signals.
MIDSCALE ERROR
Midscale error is the deviation of the actual analog output of a
given channel from the ideal output (0 V) when the twos comple-
ment input code representing half scale is loaded into the input
register of the DAC. It is expressed in mV.
INTERCHANNEL MIDSCALE MATCHING
The midscale matching specification indicates how closely the
amplitudes of the output signals of the two channels match
when the twos complement input code representing half scale is
loaded into the input register of both channels. It is expressed in
mV and is measured with half-scale output signals.
?VS
OUT
I
+VL
OUT
V
TRIM
MSB
LR
CLK
DR
AGND
SJ
RF
S
+V
L
?V
TRIM
MSB
SJ
DL
LL
DGND
AGND
OUT
V
OUT
I
R F
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REFERENCE
18-BIT
LATCH
18-BIT
D/A
18-BIT
D/A
REFERENCE
18-BIT
LATCH
AD1864
+
?
+
?
DIP Block Diagram
FUNCTIONAL DESCRIPTION
The AD1864 is a complete, monolithic, dual 18-bit audio DAC.
No external components are required for operation. As shown in
the block diagram, each chip contains two voltage references,
two output amplifiers, two 18-bit serial input registers and two
18-bit DACs.
The voltage reference section provides a reference voltage for
each DAC circuit. These voltages are produced by low-noise
bandgap circuits. Buffer amplifiers are also included. This
combination of elements produces reference voltages that are
unaffected by changes in temperature and time.
The output amplifiers use both MOS and bipolar devices and
incorporate an all NPN output stage. This design technique
produces higher slew rate and lower distortion than previous
techniques. Frequency response is also improved. When
combined with the appropriate on-chip feedback resistor, the
output op amps convert the output current to output voltages.
The 18-bit D/A converters use a combination of segmented
decoder and R-2R architecture to achieve consistent linearity
and differential linearity. The resistors which form the ladder
structure are fabricated with silicon chromium thin film. Laser
trimming of these resistors further reduces linearity errors
resulting in low output distortion.
The input registers are fabricated with CMOS logic gates.
These gates allow the achievement of fast switching speeds and
low power consumption, contributing to the low glitch and low
power dissipation of the AD1864.


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