AD1843JST datasheet(5/64 Pages) AD

No de pièce	AD1843JST

Description	Serial-Port 16-Bit SoundComm Codec

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Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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AD1843

REV. 0

–5–

Figure 1. Timing Diagrams

ANALOG OUTPUT

Min

Typ

Max

Units

LOUT1 Full-Scale Output Voltage

0.707

V rms

(RMS Values Assume Sine Wave Input)

1.8

2.0

2.2

V p-p

LOUT2 Full-Scale Single-Ended Output Voltage

0.707

V rms

(RMS Values Assume Sine Wave Input)

1.8

2.0

2.2

V p-p

LOUT2 Full-Scale Differential Output Voltage

1.414

V rms

(RMS Values Assume Sine Wave Input)

3.6

4.0

4.4

V p-p

LOUT1 Output Impedance*

600

Ω

LOUT2 Output Impedance*

1

Ω

LOUT1 External Load Impedance*

10

k

Ω

LOUT2 External Load Impedance*

2

k

Ω

MOUT External Load Impedance*

10

k

Ω

HPOUT External Load Impedance*

16

32

Ω

HPOUT THD+N (Referenced to Full Scale, 32

Ω External Load Impedance)

0.10

%

–60

dB

Output Capacitance*

15

pF

External Load Capacitance*

100

pF

CMOUT

2.10

2.25

2.40

V

External CMOUT Load Current*

10

µA

CMOUT Output Impedance*

4

k

Ω

Mute Click* (Muted Output Minus Unmuted Midscale DAC1 and DAC2 Outputs)

±5mV

SYSTEM SPECIFICATIONS

Max

Units

System Frequency Response Ripple* (Line-In to Line-Out)

1.0

dB

Differential Nonlinearity*

±1

Bit

Phase Linearity Deviation*

5

Degrees

STATIC DIGITAL SPECIFICATIONS

Min

Max

Units

High-Level Input Voltage (VIH)

Digital Inputs, Except SCLK

2.0

VDD+ 0.3

V

XTALI and SCLK

2.4

VDD+ 0.3

V

Low-Level Input Voltage (VIL)

–0.3

0.8

V

High-Level Output Voltage (VOH)

2.4

V

Low-Level Output Voltage (VOL)

0.4

V

Input Leakage Current (GO/NOGO Tested)

–10

10

µA

Output Leakage Current (GO/NOGO Tested)

–10

10

µA

TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE AND DIGITAL SUPPLY RANGE)

Min

Typ

Max

Units

Serial Data Frame Sync [SDFS] Period (t1)

(Master Mode, FRS = 1 [16 Slots per Frame], SCF = 0 [SCLK = 12.288 MHz])

20.833

µs

Frame Sync [SDFS] HI Pulse Width (t2)80

ns

Clock [SCLK] to Frame Sync [SDFS] Propagation Delay (tPD1)15

ns

Data [SDI] Input Setup Time to SCLK (tS)10

ns

Data [SDI] Input Hold Time from SCLK (tH)10

ns

Clock [SCLK] to Output Data [SDO] Valid (tDV)15

ns

Clock [SCLK] to Output Data [SDO] Three-State [High-Z] (tHZ)15

ns

Clock [SCLK] to Time Slot Output [TSO] Propagation Delay (tPD2)15

ns

RESET

and PWRDWN LO Pulse Width (tRPWL)

100

ns

t2

BIT 0

BIT 14

BIT 15

BIT 14

BIT 0

tPD1

SCLK

SDFS

SDI

SDO

tS

tH

tDV

tHZ

RESET

PWRDWN

tRPWL

15 14 13

3 2 1 0 15 14 13

tPD2

tPD1

SCLK

SDFS

SDI OR SDO

TSO

LAST

VALID

TIME SLOT

t1

15 1413

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