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AD1672AP Fiches technique(PDF) 10 Page - Analog Devices |
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AD1672AP Fiches technique(HTML) 10 Page - Analog Devices |
10 / 20 page AD1672 REV. 0 –10– The selection of the buffer is of particular concern in preserving the performance of the AD1672. The total output referred- noise contribution of the selected amplifier should be less than 200 µV rms to preserve the AD1672’s noise performance. The amplifiers harmonic distortion should be 12 dB or better in per- formance than the AD1672 over the bandwidth and signal level range of the particular application. The selected amplifier should settle to 0.01% within 70 ns. Table I lists the performance of various suitable amplifiers when configured for a gain of +1 or –1 with the AD1672 configured for ±2.5 V bipolar operation and f CLOCK = 3 MHz. The AD80xx family of high speed amplifiers are only suitable for ±2.5 V bipolar and 0 V–2.5 V unipolar operation due to their power- supply range and voltage output swing constraints. Note that the SNR, THD, and SFDR results in Tables I, II and III are for a 750 kHz full-scale (–0.5 dB) input signal. These results were determined experimentally using the AD1672 evaluation board, and hence the stated amplifier’s performance is inclusive of the AD1672. Table I. –2.5 V to +2.5 V Range ADI Part # SNR THD SFDR Gain AD8047 70.5 –67.5 –68.4 +1 AD8041 70.0 –67.3 –68.2 +1 AD8011 70.5 –67.0 –67.8 +1 AD817 70.4 –62.1 –62.9 +1 AD818 70.3 –65.0 –68.0 –1 AD811 70.3 –61.9 –63.4 +1 w/o Op Amp 70.5 –67.5 –68.4 Table II lists the performance of three high speed amplifiers which are configured for a gain of +1 or –1 with the AD1672 configured for 0 V to 5 V unipolar operation and fCLOCK = 3 MHz. Note that these amplifiers may operate at the higher power sup- ply range to achieve the 0 V to 5 V output swing. Table II. 0 V to +5 V Range Settling ADI Time (ns) Part # SNR THD to 0.01% Gain AD811 70.1 –67.6 65 +1 AD817 70.1 –68.9 70 +1 AD818 70.0 –67.4 80 –1 Table III lists the performance of two high speed amplifiers specified for single supply operation. They are configured for a gain of +1 with the AD1672 configured for 0 V to 2.5 V unipolar operation and fCLOCK = 3 MHz. The output of these amplifiers are ac coupled to the AD1672. Table III. AC Coupled 0 V to 2.5 V Range ADI Part # SNR THD SFDR AD8011 70.1 –70.0 –71.6 AD8041 69.7 –71.3 –73.4 nsec 0 160 20 40 60 80 100 120 140 4500 4000 0 2000 1500 1000 500 3000 2500 3500 Figure 14. Typical AD1672 Settling Time The AD1672 will contribute its own wideband thermal noise. As a result of the integrated wideband noise (1/4 LSB rms, referred-to-input), applying a dc analog input produces more than one code at the output. A histogram analysis of the AD1672 with a dc input is shown in Figure 15. It shows a bell shaped curve consistent with the Gaussian nature of the thermal noise. This histogram will be approximately 3 codes wide, depending on how well the input is centered on a given code and how many samples are taken. Figure 16 illustrates the AD1672’s transition noise. DEVIATION FROM CORRECT CODE – LSB 2100000 1800000 0 1200000 900000 600000 300000 1500000 +1 –1 0 2015807 13639 67324 Figure 15. Typical Grounded Histogram 100 90 0 60 30 20 10 80 70 40 50 σ = 0.25 LSB RMS CODE X CODE X ÷ 1 Figure 16. Code Probability at a Transition |
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Description similaire - AD1672AP |
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