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AD9250-170EBZ Fiches technique(PDF) 9 Page - Analog Devices

No de pièce AD9250-170EBZ
Description  14-Bit, 170 MSPS/250 MSPS, JESD204B,Dual Analog-to-Digital Converter
Download  44 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD9250-170EBZ Fiches technique(HTML) 9 Page - Analog Devices

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Data Sheet
AD9250
Rev. 0 | Page 9 of 44
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SPI TIMING REQUIREMENTS (See Figure 58)
t
DS
Setup time between the data and the rising edge of SCLK
2
ns
t
DH
Hold time between the data and the rising edge of SCLK
2
ns
t
CLK
Period of the SCLK
40
ns
t
S
Setup time between CS and SCLK
2
ns
t
H
Hold time between CS and SCLK
2
ns
t
HIGH
Minimum period that SCLK should be in a logic high state
10
ns
t
LOW
Minimum period that SCLK should be in a logic low state
10
ns
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in figures)
10
ns
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in figures)
10
ns
t
SPI_RST
Time required after hard or soft reset until SPI access is available
(not shown in figures)
500
µs
Timing Diagrams
N – 36
N – 35
N – 34
N – 33
N – 1
N + 1
SAMPLE N
ANALOG
INPUT
SIGNAL
CLK–
CLK+
CLK–
CLK+
SERDOUT1±
SERDOUT0±
SAMPLE N – 36
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 35
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 34
ENCODED INTO 2
8b/10b SYMBOLS
Figure 2. Data Output Timing
tREFS
tREFH
tREFSRF
tREFHRF
RFCLK
CLK–
CLK+
SYSREF+
SYSREF–
Figure 3. SYSREF± Setup and Hold Timing


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