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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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RT7237J Fiches technique(PDF) 13 Page - Richtek Technology Corporation |
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RT7237J Fiches technique(HTML) 13 Page - Richtek Technology Corporation |
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13 / 15 page  RT7237J 13 DS7237J-00 September 2012 www.richtek.com © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 7. Derating Curve of Maximum Power Dissipation (a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W (b) Copper Area = 10mm2, θJA = 64°C/W (c) Copper Area = 30mm2 , θJA = 54°C/W (d) Copper Area = 50mm2 , θJA = 51°C/W (e) Copper Area = 70mm2 , θJA = 49°C/W Figure 6. Thermal Resistance vs. Copper Area Layout Design 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 25 50 75 100 125 Ambient Temperature (°C) Copper Area 70mm 2 50mm 2 30mm 2 10mm 2 Min.Layout Four-Layer PCB Layout Consideration Follow the PCB layout guidelines for optimal performance of the RT7237J. Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins (VIN and GND). SW node is with high frequency voltage swing and should be kept at small area. Keep analog components away from the SW node to prevent stray capacitive noise pick-up. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT7237J. An example of PCB layout guide is shown in Figure 8 for reference. |
Numéro de pièce similaire - RT7237J |
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Description similaire - RT7237J |
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