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FAN5340UCX Fiches technique(PDF) 3 Page - Fairchild Semiconductor |
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FAN5340UCX Fiches technique(HTML) 3 Page - Fairchild Semiconductor |
3 / 12 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5340 • Rev. 1.0.1 3 Pin Configuration C1 B1 A1 A2 C3 B3 A3 C2 GND EN VLED FB VIN VOUT SW PGND Figure 3. WLCSP Package, Top View C1 B1 A1 C3 B3 A3 A2 C2 Figure 4. WLCSP Package, Bottom View P1 GND 4 3 2 1 5 6 7 8 VIN VOUT SW PGND GND EN VLED FB Figure 5. 8-Pin 3 x 3mm MLP, Top View Pin Definitions Pin # Name Description CSP MLP A1 1 GND Analog Ground . All signals are referenced to this pin. A2 2 EN Enable / PWM Brightness Control . A logic LOW on this pin shuts down the IC, disconnects the LEDs from VOUT, and reduces the current consumption of the IC. This terminal has an internal pull-down resistor of 300kΩ. A3 3 VLED LED String Output . Connected to the anode of a series string of two to four LEDs. B3 4 FB Current Feedback . The boost regulator regulates this pin to 0.5V to control the LED string current. Tie this pin via a current-setting resistor (RSET) to GND and the cathode of the LED string. C3 5 PGND Power Ground . The boost switch and gate drivers are grounded at this pin. C2 6 SW Switching Node . Tie inductor L1 from VIN to this pin. C1 7 VOUT Boost Output Voltage . Output of the boost regulator. B1 8 VIN Input Voltage . |
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Description similaire - FAN5340UCX |
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