74VHCT573ASJ_07 datasheet(5/9 Pages) FAIRCHILD

No de pièce	74VHCT573ASJ

Description	Octal D-Type Latch with 3-STATE Outputs

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Fabricant	FAIRCHILD [Fairchild Semiconductor]

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74VHCT573A Rev. 1.3

5

AC Electrical Characteristics

Notes:

7. Parameter guaranteed by design. tOSLH = |tPLH max – tPLH min|; tOSHL = |tPHL max – tPHL min|

8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating

current consumption without load. Average operating current can be obtained by the equation:

ICC (Opr.) = CPD • VCC • fIN + ICC / 8 (per F/F). The total CPD when n pcs. of the Latch operates can be

calculated by the equation: CPD(total) = 14 + 13n.

AC Operating Requirements

Symbol

Parameter

VCC (V)

Conditions

TA = +25°C

TA = –40°C

to +85°C

Units

Min.

Typ. Max. Min. Max.

tPLH, tPHL

Propagation Delay

Time (LE to On)

5.0 ± 0.5

CL = 15pF

7.7

12.3

1.0

13.5

ns

CL = 50pF

8.5

13.3

1.0

14.5

tPLH, tPHL

Propagation Delay

Time (D to On)

5.0 ± 0.5

CL = 15pF

5.1

8.5

1.0

9.5

ns

CL = 50pF

5.9

9.5

1.0

10.5

tPZL, tPZH

3-STATE Output

Enable Time

5.0 ± 0.5 RL = 1kΩ CL = 15pF

6.3

10.9

1.0

12.5

ns

CL = 50pF

7.1

11.9

1.0

13.5

tPLZ, tPHZ

3-STATE Output

Disable Time

5.0 ± 0.5 RL = 1kΩ CL = 50pF

8.8

11.2

1.0

12.0

ns

tOSLH, tOSHL Output to Output

Skew

5.0 ± 0.5 (7)

1.0

ns

CIN

Input Capacitance

VCC = Open

4

10

pF

COUT

Output Capacitance

VCC = 5.0V

6

pF

CPD

Power Dissipation

Capacitance

(8)

25

pF

Symbol

Parameter

VCC (V)

TA = +25°C

TA = –40°C to +85°C

Units

Min.

Typ.

Max.

Min.

Max.

tW(H)

Minimum Pulse Width (LE)

5.0 ± 0.5

6.5

8.5

ns

tS

Minimum Set-Up Time

5.0 ± 0.5

1.5

ns

tH

Minimum Hold Time

5.0 ± 0.5

3.5

ns

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