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74LCX245BQX Fiches technique(PDF) 2 Page - Fairchild Semiconductor |
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74LCX245BQX Fiches technique(HTML) 2 Page - Fairchild Semiconductor |
2 / 14 page ©1994 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX245 Rev. 1.11.0 2 Connection Diagrams Pin Assignments for SOIC, SOP, SSOP, and TSSOP Pin Assignment for DQFN (Top Through View) Pin Description Logic Symbol Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Note: 3. Unused bus terminals during HIGH Z State must be held HIGH or LOW. Logic Diagram Pin Names Description OE Output Enable Input T/R Transmit/Receive Input A0–A7 Side A Inputs or 3-STATE Outputs B0–B7 Side B Inputs or 3-STATE Outputs Inputs Outputs OE T/R LL Bus B0 – B7 Data to Bus A0 – A7 LH Bus A0 – A7 Data to Bus B0 – B7 HX HIGH Z State on A0 – A7, B0 – B7 (3) |
Numéro de pièce similaire - 74LCX245BQX_08 |
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Description similaire - 74LCX245BQX_08 |
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