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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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WM8961 Fiches technique(PDF) 19 Page - Wolfson Microelectronics plc |
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WM8961 Fiches technique(HTML) 19 Page - Wolfson Microelectronics plc |
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19 / 116 page  WM8961 Pre-Production w PP, August 2009, Rev 3.1 19 DEVICE DESCRIPTION INTRODUCTION The WM8961 is a low power audio CODEC offering a combination of high quality audio, advanced features, low power and small size. These characteristics make it ideal for portable digital audio applications with stereo speaker and headphone outputs such as games consoles, portable media players and multimedia phones. A flexible input configuration supports a single-ended stereo microphone interface. A boost amplifier is available for additional gain on the microphone inputs. A programmable gain amplifier (PGA) with an automatic level control (ALC) function can be used to maintain a constant microphone recording volume. Stereo class D speaker drivers can provide >1W per channel into 8 Ω loads. BTL configuration provides high power output and excellent PSRR. Highly flexible output speaker boost settings provide fully internal level-shifting of analogue output signals, allowing speaker output power to be maximised while minimising other analogue supply currents, and requiring no additional components. A dual mode (Level Shifting or Inverting Mode) charge pump generates split supplies for the headphone output amplifiers allowing these to be ground referenced. A DC servo to remove offsets from the headphone outputs, low leakage and a user controlled power- up/power-down Control Sequencer provides powerful pop and click suppression mechanisms which enable direct battery connection. These anti-pop/click mechanisms, and no requirement for any external DC blocking capacitors to the headphone, results in a reduced external component count and reduced power consumption in portable battery-powered applications. The hi-fi quality stereo ADC and DAC uses a 24-bit, low-order over-sampling architecture to deliver optimum performance. ADC and DAC operate at the same sample rate. The WM8961 has a configurable digital audio interface where ADC data can be read and digital audio playback data fed to the DAC. It supports a number of audio data formats including I 2S, DSP Mode (a burst mode in which frame sync plus two data packed words are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes. In PCM mode A-law and μ- law companding is supported. The SYSCLK (internal system clock) provides clocking for all internal functions. SYSCLK is derived directly from the MCLK pin. All MCLK frequencies typically used in portable systems are supported for sample rates between 8 kHz and 48 kHz. The ADC and DAC must be configured to operate at the same sample rate. A flexible switching clock for the class D speaker drivers (synchronous with the audio DSP clocks for best performance) is also derived from SYSCLK. To allow full software control over all its features, the WM8961 uses a 2 wire serial control interface, with full read-back capability on all registers. It is fully compatible with, and an ideal partner to, a wide range of industry standard microprocessors, controllers and DSPs. Unused functions can be disabled via software to save power, while low leakage currents extend standby and off time in portable battery-powered applications. |
Numéro de pièce similaire - WM8961 |
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Description similaire - WM8961 |
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