© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FIN224C • Rev. 1.0.9

7

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Phase Lock Loop Stabilization Time

200

µs

PLL Disable Time Loss of Clock

30

µs

AC Deserializer, DIRI = 0 Specifications

CKS

Allowed DS-CKS Input Signal Skew

-150

150

ps

CKP Out Low Time

CKREF = STROBE, a = (1/f)/13

13a-3

13a+3

ns

CKP Out High Time

13a-3

13a+13

ns

Data Valid to CKP Low

8a-6

8a+1

ns

Output Rise Time (20% to 80%)

18

ns

Output Fall Time (20% to 80%)

18

ns

AC Enable and Disable Timing

Deserializer Disable Time

25

ns

Deserializer Enable Time

2

µs

Serializer Disable Time

25

ns

Serializer Enable Time

65

ns

Notes:

2.

Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of DSO. Signals are

edge aligned. Both outputs should have identical load condtions for this test to be valid.

3.

If CKREF is not equal to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle. The low time of

CKP remains 13 bit times.