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ADC08D502 Fiches technique(PDF) 11 Page - Texas Instruments

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No de pièce ADC08D502
Description  ADC08D502 High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
Download  43 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

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ADC08D502
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SNOSC85 – AUGUST 2012
Converter Electrical Characteristics (continued)
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG =
Floating, Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω
Differential. Boldface limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted.
(1) (2)
Typical
Limits
Units
Symbol
Parameter
Conditions
(3)
(3)
(Limits)
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Error Match
1
LSB
Positive Full-Scale Error Match
Zero offset selected in Control Register
1
LSB
Negative Full-Scale Error Match
Zero offset selected in Control Register
1
LSB
Phase Matching (I, Q)
FIN = 1.0 GHz
< 1
Degree
Crosstalk from I (Aggressor) to Q
Aggressor = 867 MHz F.S.
X-TALK
−71
dB
(Victim) Channel
Victim = 100 MHz F.S.
Crosstalk from Q (Aggressor) to I
Aggressor = 867 MHz F.S.
X-TALK
-71
dB
(Victim) Channel
Victim = 100 MHz F.S.
CLOCK INPUT CHARACTERISTICS
0.4
VP-P (min)
Sine Wave Clock
0.6
2.0
VP-P (max)
VID
Differential Clock Input Level
0.4
VP-P (min)
Square Wave Clock
0.6
2.0
VP-P (max)
II
Input Current
VIN = 0 or VIN = VA
±1
µA
Differential
0.02
pF
CIN
Input Capacitance (7) (8)
Each input to ground
1.5
pF
DIGITAL CONTROL PIN CHARACTERISTICS
VIH
Logic High Input Voltage
(9)
0.85 x VA
V (min)
VIL
Logic Low Input Voltage
(9)
0.15 x VA
V (max)
CIN
Input Capacitance (10) (11)
Each input to ground
1.2
pF
DIGITAL OUTPUT CHARACTERISTICS
400
mVP-P (min)
Measured differentially, OutV = VA,
710
VBG = Floating,
(12)
920
mVP-P (max)
VOD
LVDS Differential Output Voltage
280
mVP-P (min)
Measured differentially, OutV = GND,
510
VBG = Floating,
(12)
720
mVP-P (max)
Change in LVDS Output Swing
Δ VO DIFF
±1
mV
Between Logic Levels
VOS
Output Offset Voltage, see Figure 1
VBG = Floating
800
mV
VOS
Output Offset Voltage, see Figure 1
VBG = VA
(12)
1200
mV
Output Offset Voltage Change
Δ VOS
±1
mV
Between Logic Levels
IOS
Output Short Circuit Current
Output+ & Output- connected to 0.8V
−4
mA
ZO
Differential Output Impedance
100
Ohms
VOH
Cal_Run High level output
IOH = -400uA
(13)
1.65
1.5
V
VOL
Cal_Run Low level output
IOH = 400uA
(13)
0.15
0.3
V
POWER SUPPLY CHARACTERISTICS
(7)
The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF
each pin to ground are isolated from the die capacitances by lead and bond wire inductances.
(8)
This parameter is guaranteed by design and is not tested in production.
(9)
This parameter is guaranteed by design and/or characterization and is not tested in production.
(10) This parameter is guaranteed by design and is not tested in production.
(11) The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated
from the die capacitances by lead and bond wire inductances.
(12) Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mv (typical), as shown in the VOS specification above.
Tying VBG to the supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).
(13) This parameter is guaranteed by design and/or characterization and is not tested in production.
Copyright © 2012, Texas Instruments Incorporated
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