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TC74VHC175FK Fiches technique(PDF) 1 Page - Toshiba Semiconductor |
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TC74VHC175FK Fiches technique(HTML) 1 Page - Toshiba Semiconductor |
1 / 10 page TC74VHC175F/FT/FK 2012-02-29 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC175F,TC74VHC175FT,TC74VHC175FK Quad D-Type Flip Flop with Clear The TC74VHC175 is an advanced high speed CMOS QUAD D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These four flip-flops are controlled by a clock input (CK) and a clear input ( CLR ). The information data applied to the D inputs (D1 thru D4) are transferred to the outputs (Q1 thru Q4 and 1 Q thru 4 Q ) on the positive-going edge of the clock pulse. When the CLR input is held low, the Q outputs are at the low logic level and the Q outputs are at the high logic level, regardless of other input conditions. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features • High speed: fmax = 210 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Power down protection is provided on all inputs. • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Low noise: VOLP = 0.8 V (max) • Pin and function compatible with 74ALS175 Weight SOP16-P-300-1.27A : 0.18 g (typ.) TSSOP16-P-0044-0.65A : 0.06 g (typ.) VSSOP16-P-0030-0.50 : 0.02 g (typ.) TC74VHC175F TC74VHC175FT TC74VHC175FK |
Numéro de pièce similaire - TC74VHC175FK_12 |
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Description similaire - TC74VHC175FK_12 |
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