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SLAS753D Fiches technique(PDF) 9 Page - Texas Instruments |
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SLAS753D Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 44 page MSP430G22x0 www.ti.com SLAS753D – JANUARY 2012 – REVISED AUGUST 2012 Special Function Registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: Bit can be read and written. rw-0,1: Bit can be read and written. It is reset or set by PUC. rw-(0,1): Bit can be read and written. It is reset or set by POR. SFR bit is not present in device. Table 7. Interrupt Enable Register 1 and 2 Address 7 6 5 4 3 2 1 0 00h ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE Oscillator fault interrupt enable. Set to 0. NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable Address 7 6 5 4 3 2 1 0 01h Table 8. Interrupt Flag Register 1 and 2 Address 7 6 5 4 3 2 1 0 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. OFIFG Flag set on oscillator fault. The XIN/XOUT pins are not available as device terminals. PORIFG Power-On Reset interrupt flag. Set on VCC power-up. RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. NMIIFG Set by RST/NMI pin Address 7 6 5 4 3 2 1 0 03h Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9 |
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