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SN74ACT8999 Fiches technique(PDF) 4 Page - Texas Instruments |
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SN74ACT8999 Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 29 page SN54ACT8999, SN74ACT8999 SCANPATH SELECTORS WITH 8BIT BIDIRECTIONAL DATA BUSES SCANCONTROLLED IEEE STD 1149.1 (JTAG) TAP MULTIPLEXERS SCAS158D − JUNE 1990 − REVISED DECEMBER 1996 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions TERMINAL NAME I/O DESCRIPTION DCI I Device condition input. DCI receives interrupt and protocol signals from an RBC and/or the secondary scan path(s). When the counter register is instructed to count up or down, DCI is configured as the counter clock. DCO O Device condition output. DCO is configured by the control register to output protocol and interrupt signals to a PBC. It also can be configured by the control register to output an error signal if the instruction register or select register are loaded with invalid values. DCO is further configured by the control register as: Active high or active low (reset condition = active low) Open drain or 3-state (reset condition = open drain) DTCK O Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s). DTDI I Device test data input. DTDI receives the serial test data output of the selected secondary scan path. An internal pullup forces DTDI to a high logic level if it is left unconnected. DTDO O Device test data output. DTDO outputs serial test data to the TDI input(s) of the secondary scan path(s). DTMS1 DTMS2 DTMS3 DTMS4 O Device test mode select 1−4. Either one or none of these four outputs can be selected to follow TMS or OTMS to include a secondary scan path in the primary scan path. The unselected DTMS outputs can be independently set to a static high or low logic level. The TMS circuit monitors input from the select register to determine the configuration of the DTMS outputs. DTRST O Device test reset. This active-low output transmits a reset signal to the secondary scan path(s). DTRST can be asserted by a bit in the control register or by setting TRST low. GND Ground ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 I/O Identification 1−8. This 8-bit data bus can be used to communicate with an RBC and pass data and control instructions. By wiring pullup and pulldown resistors to these terminals, one of 255 unique identification codes can be assigned to the device to allow a test controller to determine the identity of the subsystem under test. MCI I Master condition input. MCI receives interrupt and protocol singals from a PBC. MCO O Master condition output. MCO transmits interrupt and protocol signals to an RBC and/or the secondary scan path(s). MCO also outputs an active-low error signal during the Pause-DR TAP state if an RBC loads an invalid value in the select register. OTMS I Optional test mode select. OTMS can be used instead of TMS to control the select register. This is useful when a remote bus controller is available to control the secondary scan path(s). An internal pullup forces OTMS to a high level if left unconnected. TCK I Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the ’ACT8999 except for the count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs change on the falling edge of TCK. TDI I Test data input. One of four terminals required by IEEE Standard 1149.1. TDI is the serial input for shifting information into the instruction register or selected data register. TDI is typically driven by the TDO output of the primary bus controller. An internal pullup forces TDI to a high level if it is left unconnected. TDO O Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting information out of the instruction register or selected data register. TDO is typically connected to the TDI input of the next scannable device in the primary scan path. TMS I Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of TCK directs the ’ACT8999 through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. TRST I Test reset. This active-low input inplements the optional reset terminal of IEEE Standard 1149.1. When asserted, TRST causes the ’ACT8999 to go to the Test-Logic-Reset state and configure the instruction register and data registers to their power-up values. TRST is also output without inversion via DTRST. An internal pullup forces TRST to a high level if left unconnected. VCC Supply voltage |
Numéro de pièce similaire - SN74ACT8999 |
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Description similaire - SN74ACT8999 |
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