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SM320C50-EP Fiches technique(PDF) 2 Page - Texas Instruments |
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SM320C50-EP Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 29 page SM320C50EP DIGITAL SIGNAL PROCESSOR SGUS040A − AUGUST 2002 − REVISED JANUARY 2006 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 description (continued) A number of enhancements to the basic C2x architecture give the C50 a minimum 2 × performance over the previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory. The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 µA. A low-logic level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode. The SM320C50-EP is available with a clock speed of 66 MHz providing a 30-ns cycle time and a clock speed of 80 MHz providing a 25-ns cycle time. The available options are listed in Table 1. Table 1. Available Options PART NUMBER SPEED SUPPLY VOLTAGE TOLERANCE PACKAGE SM320C50PQM66EP 30 ns cycle time ±5% Plastic Quad flat package SM320C50PQI80EP 25 ns cycle time ±5% Plastic Quad flat package |
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Description similaire - SM320C50-EP |
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