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SN74ALVC16901 Fiches technique(PDF) 1 Page - Texas Instruments |
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SN74ALVC16901 Fiches technique(HTML) 1 Page - Texas Instruments |
1 / 9 page SN74ALVC16901 18BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCAS276A − NOVEMBER 1993 − REVISED JULY 1995 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D Member of the Texas Instruments Widebus+ Family D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process D UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode D Simultaneously Generates and Checks Parity D Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors D Packaged in Thin Shrink Small-Outline (DGG) Package description This 18-bit (dual-octal) noninverting registered transceiver is designed for 2.7-V to 3.6-V VCC operation. The SN74ALVC16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction. The SN74ALVC16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When SEL is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVC16901 is available in TI’s thin shrink small-outline (DGG) package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN74ALVC16901 is characterized for operation from − 40 °C to 85°C. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1CLKENAB LEAB CLKAB 1ERRA 1APAR GND 1A1 1A2 1A3 VCC 1A4 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 2A5 VCC 2A6 2A7 2A8 GND 2APAR 2ERRA OEAB SEL 2CLKENAB 1CLKENBA LEBA CLKBA 1ERRB 1BPAR GND 1B1 1B2 1B3 VCC 1B4 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 2B5 VCC 2B6 2B7 2B8 GND 2BPAR 2ERRB OEBA ODD/EVEN 2CLKENBA Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated. |
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Description similaire - SN74ALVC16901 |
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