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CDCVF2505 Fiches technique(PDF) 4 Page - Texas Instruments |
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CDCVF2505 Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 14 page CDCVF2505 3.3V CLOCK PHASELOCK LOOP CLOCK DRIVER SCAS640E − JULY 2000 − REVISED MARCH 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN NOM MAX UNIT fclk Clock frequency 24 200 MHz Input clock duty cycle 24 MHz − 85 MHz (see Note 4) 30% 85% Input clock duty cycle 86 MHz − 200 MHz 40% 50% 60% Stabilization time (see Note 5) 100 µs NOTES: 4. Ensured by design but not 100% production tested. 5. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VDD MIN TYP† MAX UNIT VIK Input voltage II = −18 mA 3 V −1.2 V IOH = −100 µA MIN to MAX VDD−0.2 VOH High-level output voltage IOH = −12 mA 3 V 2.1 V VOH High-level output voltage IOH = −6 mA 3 V 2.4 V IOL = 100 µA MIN to MAX 0.2 VOL Low-level output voltage IOL = 12 mA 3 V 0.8 V VOL Low-level output voltage IOL = 6 mA 3 V 0.55 V IOH High-level output current VO = 1 V 3 V −27 mA IOH High-level output current VO = 1.65 V 3.3 V −36 mA IOL Low-level output current VO = 2 V 3 V 27 mA IOL Low-level output current VO = 1.65 V 3.3 V 40 mA II Input current VI = 0 V or VDD ±5 µA Ci Input capacitance VI = 0 V or VDD 3.3 V 4.2 pF Co Output capacitance Yn VI = 0 V or VDD 3.3 V 2.8 pF Co Output capacitance CLKOUT VI = 0 V or VDD 3.3 V 5.2 pF † All typical values are at respective nominal VDD and 25°C. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, VDD = 3.3 V ± 0.3 V (see Note 5) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tpd Propagation delay (normalized (see Figure 3) CLKIN to Yn, f= 66 MHz to 200 MHz −150 150 ps tsk(o) Output skew (see Note 6) Yn to Yn 150 ps tc(jit_cc) Jitter (cycle to cycle) (see Figure 5) f = 66 MHz to 200 MHz 70 150 ps tc(jit_cc) Jitter (cycle to cycle) (see Figure 5) f = 24 MHz to 50 MHz 200 400 ps odc Output duty cycle (see Figure 4) f = 24 MHz to 200 MHz at 50% VDD 45% 55% tr Rise time VO = 0.4 V to 2 V 0.5 2 ns tf Fall time VO = 2 V to 0.4 V 0.5 2 ns † All typical values are at respective nominal VDD and 25°C. NOTE 6: The tsk(o) specification is only valid for equal loading of all outputs. |
Numéro de pièce similaire - CDCVF2505 |
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Description similaire - CDCVF2505 |
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