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TPS71928-28DRVRG4 Fiches technique(PDF) 10 Page - Texas Instruments |
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TPS71928-28DRVRG4 Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 24 page APPLICATION INFORMATION Board Layout Recommendations to Improve Internal Current Limit TPS718xx TPS719xx GND EN1 EN2 OUT2 IN OUT1 V IN V OUT V OUT 1 F m 1 F m 1 F m 2.7V 6.5V - 0.9V 3.6V - 0.9V 3.6V - On Off On Off Shutdown Input and Output Capacitor Requirements t=3 60 R L ´ 60+R L C OUT ´ Dropout Voltage TPS718xx TPS719xx SBVS088C – FEBRUARY 2007 – REVISED MAY 2008..................................................................................................................................................... www.ti.com The TPS718xx/TPS719xx belong to a family of new generation LDO regulators that use innovative PSRR and Noise Performance circuitry to achieve ultra-wide bandwidth and high loop gain, resulting in extremely high PSRR (up to To improve ac performance such as PSRR, output 1MHz) at very low headroom (VIN – VOUT). These noise, and transient response, it is recommended that features, combined with low noise, two independent the board be designed with separate ground planes enables, low ground pin current and ultra-small for VIN and VOUT, with each ground plane connected packaging, make this part ideal for portable only at the GND pin of the device. In addition, the applications. This family of regulators offer ground connection for the output capacitor should sub-bandgap output voltages, current limit and connect directly to the GND pin of the device. High thermal protection, and is fully specified from –40 °C ESR capacitors may degrade PSRR. to +125 °C. Figure 22 shows the basic circuit connections. The TPS718xx/TPS719xx internal current limits help protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time. The PMOS pass element in the TPS718xx/TPS719xx has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current may be appropriate. Figure 22. Typical Application Circuit The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. Although an input capacitor is not required for When shutdown capability is not required, EN can be stability, it is good analog design practice to connect connected to IN. The TPS719 with internal active a 0.1 µF to 1.0µF low equivalent series resistance output pulldown circuitry discharges the output with a (ESR) capacitor across the input supply near the time constant (t) of: regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is located close to the power source. If source with: impedance is not sufficiently low, a 0.1 µF input RL = output load resistance capacitor may be necessary to ensure stability. COUT = output capacitance The TPS718xx/TPS719xx are designed to be stable with standard ceramic capacitors of values 1.0 µF or larger at the output. X5R- and X7R-type capacitors The TPS718xx/TPS719xx use a PMOS pass are best because they have minimal variation in value transistor to achieve low dropout. When (VIN – VOUT) and ESR over temperature. Maximum ESR should be is less than the dropout voltage (VDO), the PMOS <1.0 Ω. pass device is in its linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device behaves like a resistor in dropout. 10 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS718xx TPS719xx |
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