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TPS71202-EP Fiches technique(PDF) 10 Page - Texas Instruments

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No de pièce TPS71202-EP
Description  DUAL, 250-mA OUTPUT, ULTRA-LOW NOISE, HIGH PSRR, LOW-DROPOUT LINEAR REGULATOR
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TPS71202-EP Fiches technique(HTML) 10 Page - Texas Instruments

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C1 +
(3
105)
(R1 ) R2)
(R1
R2)
(pF)
V
OUT + VREF
1 )
R1
R2
R1 +
V
OUT
V
REF
* 1
R2
VOUT
1.225 V
1.5 V
2.5 V
3.0 V
3.3 V
4.75 V
R1/R3
Short
7.15 k
31.6 k
43.2 k
49.9 k
86.6 k
R2/R4
Open
30.1 k
30.1 k
30.1 k
30.1 k
30.1 k
Output Voltage Programming Guide
C1/C2
Open
100 pF
22 pF
15 pF
15 pF
15 pF
TPS71202
GND
EN2
FB2
NR
IN
OUT1
FB1
EN1
OUT2
V
IN
V
OUT1
V
OUT2
0.1
µF
2.2
µF
2.2
µF
0.01
µF
C1
R1
C2
R3
R2
R4
TPS71202-EP
SGLS395A – OCTOBER 2008 – REVISED SEPTEMBER 2010
www.ti.com
PROGRAMMING THE TPS71202
For voltages
≤ 1.8 V, the value of this capacitor
ADJUSTABLE LDO REGULATOR
should be 100 pF. For voltages > 1.8 V, the
approximate value of this capacitor can be calculated
The output voltage of the TPS71202 dual adjustable
as Equation 3:
regulator is programmed using an external resistor
divider, as shown in Figure 24. The output voltage is
calculated using Equation 1:
(3)
blank
(1)
The suggested value of this capacitor for several
where VREF = 1.225 V (the internal reference
resistor ratios is shown in Figure 24. If this capacitor
voltage).
is not used (such as in a unity-gain configuration) or if
an output voltage
≤ 1.8 V is chosen, then the
Resistors
R2
and
R4
should
be
chosen
for
minimum recommended output capacitor is 4.7 mF
approximately a 40-mA divider current. Lower value
instead of 2.2 mF.
resistors
can
be
used
for
improved
noise
performance but consume more power. Higher values
DROPOUT VOLTAGE
should be avoided because leakage current at FB
increases the output voltage error. The recommended
The TPS712xx uses a PMOS pass transistor to
design procedure is to choose R2 = 30.1 k
Ω to set
achieve extremely low dropout. When (VIN - VOUT) is
the divider current at 40 mA, and then calculate R1
less than the dropout voltage (VDO), the PMOS pass
using Equation 2:
device is in its linear region of operation and the
input-to-output resistance is the RDS, ON of the PMOS
pass element. Dropout voltages at lower currents can
(2)
be approximated by calculating the effective RDS, ON
of the pass element and multiplying that resistance by
To improve the stability and noise performance of the
the load current. RDS, ON of the pass element can be
adjustable version, a small compensation capacitor
obtained by dividing the dropout voltage by the rated
can be placed between OUT and FB.
output current.
Figure 24. Adjustable LDO Regulator Programming
10
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Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS71202-EP


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