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TPS62110HPWP Fiches technique(PDF) 5 Page - Texas Instruments |
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TPS62110HPWP Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 25 page TPS62110-HT www.ti.com SLVSAO9B – DECEMBER 2010 – REVISED FEBRUARY 2011 ELECTRICAL CHARACTERISTICS (continued) VI = 12 V, VO = 3.3 V, IO = 600 mA, EN = VI TA = -55°C to 125°C TA = 175°C PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX OSCILLATOR fS Oscillator frequency 900 1000 1100 900 1000 1100 kHz f(SYNC) Synchronization range CMOS-logic clock signal on SYNC pin 800 1410 800 1410 kHz SYNC high-level input VIH 1.5 1.5 V voltage SYNC low-level input VIL 0.3 0.3 V voltage Ilkg SYNC input leakage current SYNC = GND or VIN 0.01 0.2 0.07 0.2 μA SYNC trip-point hysteresis 170 170 mV SYNC input current 0.6 V ≤ V(SYNC) ≤ 4 V 10 20 5 20 µA Duty cycle of external clock 30 90 30 90 % signal OUTPUT Adjustable output voltage VO 1.153 16 1.153 16 V range VFB Feedback voltage 1.153 1.153 V FB leakage current 10 100 290 2100 nA Feedback voltage tolerance VI = 3.1 V to 17 V, –6 7.5 –7 8 % (3) 0 mA < IO < 1500 mA (4) VI ≥ 3 V (once undervoltage lockout voltage 100 100 exceeded) VI ≥ 3.5 V 500 500 IO Maximum output current mA VI ≥ 4.3 V 1200 1100 VI ≥ 6 V 1500 1500 Current into internal voltage divider for fixed voltage 5 5 μA versions VI = 7.2 V, VO = 3.3 V, IO = 600 mA 92 82 η Efficiency % VI = 12 V, VO = 5 V, IO = 600 mA 92 82 Duty cycle range for main at 1 MHz 10 100 10 100 % switches(3) Minimum ton time for main 100 100 ns switch Start-up time IO = 800 mA, VI = 12 V, VO = 3.3 V 1 ms (3) Not production tested (4) The maximum output current depends on the input voltage. See the maximum output current for further restrictions on the minimum input voltage. © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS62110-HT |
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