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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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TPA2054D4A Fiches technique(PDF) 5 Page - Texas Instruments |
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TPA2054D4A Fiches technique(HTML) 5 Page - Texas Instruments |
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5 / 30 page  TPA2054D4A www.ti.com SLOS666 – MAY 2010 DISSIPATION RATINGS PACKAGE TA < 25°C DERATING FACTOR TA = 70°C TA = 85°C YZK (WCSP) 1.12 W 9 mW/°C 720 mW 585 mW RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Class-D supply voltage, PVDD 2.5 5.5 V Charge pump supply voltage, VDDHP 2.5 5.5 V I2C supply voltage, DVDD 1.7 3.3 V VIH High-level input voltage SDA, SCL, RESET, DVDD = 1.8 V 1.3 V SDA, SCL, RESET, DVDD = 3.3 V 3.0 VIL Low-level input voltage SDA, SCL, RESET, DVDD = 1.8 V 0.3 V SDA, SCL, RESET, DVDD = 3.3 V TA Operation free-air temperature –40 85 °C ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Power supply rejection ratio VDD = 2.5 V to 5.5 V, Single-ended mode 48 75 dB (Class-D amplifiers) DC Power supply rejection ratio VDD = 2.5 V to 5.5 V, Single-ended mode 60 80 dB (headphone amplifiers) High-level input current (SDA, SCL, 1 mA RESET) Low-level input current (SDA, SCL, 1 mA RESET) AVDD Power on reset ON threshold 2.0 2.3 V AVDD Power on reset hysteresis 0.2 V VDD = 5.5 V, Class-D and Headphone amplifiers active, no load 15.8 20 mA VDD = 4.2 V, Class-D active, Headphone deactivated, no load 7.5 10.5 mA VDD = 4.2 V, Headphone active, Class-D deactivated, no load 10 13.5 mA Supply current VDD = 2.5 V to 5.5 V, RESET ≥ VIH, SWS = 1 2.5 4 mA (software shutdown mode) VDD = 2.5 V to 5.5 V, RESET ≤ 0.3 V (hard shutdown mode) 0.2 2 mA TIMING CHARACTERISTICS For I 2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSCLN Frequency, SCL No wait states 400 kHz tW(H) Pulse duration, SCL high 0.6 ms tW(L) Pulse duration, SCL low 1.3 ms tsu1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 10 ns t(buf) Bus free time between stop and start condition 1.3 ms tsu2 Setup time, SCL to start condition 0.6 ms th2 Hold time, start condition to SCL 0.6 ms tsu3 Setup time, SCL to stop condition 0.6 ms Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPA2054D4A |
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