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ADC1004S040 Fiches technique(PDF) 8 Page - Integrated Device Technology |
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ADC1004S040 Fiches technique(HTML) 8 Page - Integrated Device Technology |
8 / 18 page ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 8 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz ts(LH) LOW to HIGH settling time full-scale square wave; see Figure 6 [6] - 1.5 3.0 ns ts(HL) HIGH to LOW settling time - 1.5 3.0 ns Harmonics (fclk = 40 MHz); see Figure 7 and 8 1H first harmonic level fi = 4.43 MHz - - 0 dB 2H second harmonic level fi = 4.43 MHz - 75 65 dB 3H third harmonic level fi = 4.43 MHz - 72 65 dB THD total harmonic distortion fi = 4.43 MHz - 64 - dB Signal-to-noise ratio; see Figure 7 and 8[7] S/N signal-to-noise ratio full scale; without harmonics; fclk = 40 MHz; fi = 4.43 MHz 55 58 - dB Effective bits; see Figure 7 and 8[7] ENOB effective number of bits ADC1004S030TS; fclk = 30 MHz fi = 4.43 MHz - 9.4 - bit fi = 7.5 MHz - 9.1 - bit ADC1004S040TS; fclk = 40 MHz fi = 4.43 MHz - 9.4 - bit fi = 7.5 MHz - 9.0 - bit fi = 10 MHz - 8.9 - bit fi = 15 MHz - 8.1 - bit ADC1004S050TS; fclk = 50 MHz fi = 4.43 MHz - 9.3 - bit fi = 7.5 MHz - 8.9 - bit fi = 10 MHz - 8.8 - bit fi = 15 MHz - 8.0 - bit Two-tone intermodulation[8] IM intermodulation suppression fclk = 40 MHz - 69 - dB Bit error rate BER bit error rate fclk = 40 MHz; fi = 4.43 MHz; VI = 16 LSB at code 512 - 1013 - times/samples Differential gain[9] Gdif differential gain fclk = 40 MHz; PAL modulated ramp - 0.8 - % Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to +70 C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
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