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SM320DM6446-HIREL Fiches technique(PDF) 1 Page - Texas Instruments

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No de pièce SM320DM6446-HIREL
Description  Digital Media System-on-Chip
Download  228 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

SM320DM6446-HIREL Fiches technique(HTML) 1 Page - Texas Instruments

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1
Digital Media System-on-Chip (DMSoC)
1.1 Features
SM320DM6446
Digital Media System-on-Chip
www.ti.com
SPRS607A – JUNE 2009 – REVISED JUNE 2009
• High-Performance Digital Media SoC
• ARM926EJ-S Core
594-MHz C64x+™ Clock Rates
Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
297-MHz ARM926EJ-S™ Clock Rates
DSP Instruction Extensions and Single
Eight 32-Bit C64x+ Instructions/Cycle
Cycle MAC
4752 C64x+ MIPS
ARM® Jazelle® Technology
Fully Software-Compatible With C64x /
EmbeddedICE-RT™ Logic for Real-Time
ARM9™
Debug
Extended Temperature Devices Available
• ARM9 Memory Architecture
• Advanced Very-Long-Instruction-Word (VLIW)
16K-Byte Instruction Cache
TMS320C64x+™ DSP Core
8K-Byte Data Cache
Eight Highly Independent Functional Units
16K-Byte RAM
• Six ALUs (32-/40-Bit), Each Supports
8K-Byte ROM
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Embedded Trace Buffer™ (ETB11™) With 4KB
• Two Multipliers Support Four 16 x 16-Bit
Memory for ARM9 Debug
Multiplies (32-Bit Results) per Clock
• Endianness: Little Endian for ARM and DSP
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
• Video Processing Subsystem
Results) per Clock Cycle
Front End Provides:
Load-Store Architecture With Non-Aligned
• CCD and CMOS Imager Interface
Support
• BT.601/BT.656 Digital YCbCr 4:2:2
64 32-Bit General-Purpose Registers
(8-/16-Bit) Interface
Instruction Packing Reduces Code Size
• Preview Engine for Real-Time Image
All Instructions Conditional
Processing
Additional C64x+™ Enhancements
• Glueless Interface to Common Video
• Protected Mode Operation
Decoders
• Exceptions Support for Error Detection
• Histogram Module
and Program Redirection
• Auto-Exposure, Auto-White Balance and
• Hardware Support for Modulo Loop
Auto-Focus Module
Operation
• Resize Engine
• C64x+ Instruction Set Features
Resize Images From 1/4x to 4x
Byte-Addressable (8-/16-/32-/64-Bit Data)
Separate Horizontal/Vertical Control
8-Bit Overflow Protection
Back End Provides:
Bit-Field Extract, Set, Clear
• Hardware On-Screen Display (OSD)
Normalization, Saturation, Bit-Counting
• Four 54-MHz DACs for a Combination of
Compact 16-Bit Instructions
Composite NTSC/PAL Video
Additional Instructions to Support Complex
Luma/Chroma Separate Video
Multiplies
(S-video)
• C64x+ L1/L2 Memory Architecture
Component (YPbPr or RGB) Video
32K-Byte L1P Program RAM/Cache (Direct
(Progressive)
Mapped)
• Digital Output
80K-Byte L1D Data RAM/Cache (2-Way
8-/16-bit YUV or up to 24-Bit RGB
Set-Associative)
HD Resolution
64K-Byte L2 Unified Mapped RAM/Cache
Up to 2 Video Windows
(Flexible RAM/Cache Allocation)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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