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SM320C6712C-EP Fiches technique(PDF) 7 Page - Texas Instruments

No de pièce SM320C6712C-EP
Description  FLOATING-POINT DIGITAL SIGNAL PROCESSORS
Download  109 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

SM320C6712C-EP Fiches technique(HTML) 7 Page - Texas Instruments

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SM320C6712EP, SM320C6712CEP, SM320C6712DEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSORS
SGUS055 − SEPTEMBER 2004
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
functional block and CPU (DSP core) diagram
Enhanced
DMA
Controller
(16 channel)
Test
C67x CPU (DSP Core)
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-Down
Logic
.L1† .S1† .M1† .D1
.D2 .M2† .S2† .L2†
16
SDRAM
ROM/FLASH
SBSRAM
I/O Devices
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control
Logic
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
C6712/C6712C/C6712D Digital Signal Processors
† In addition to fixed-point instructions, these functional units execute floating-point instructions.
‡ The C6712C/C6712D device has a software-configurable PLL (with x4 through x25 multiplier and /1 through /32 divider) and a PLL
Controller which is different from the hardware PLL peripheral on the C6712 device.
§ Applicable to the C6712C/C6712D device only
L2
Memory
4 Banks
64K Bytes
Total
PLL‡
Timer 0
External
Memory
Interface
(EMIF)
Multichannel
Buffered
Serial Port 1
(McBSP1)
Multichannel
Buffered
Serial Port 0
(McBSP0)
SRAM
Timer 1
Interrupt
Selector
Boot
Configuration
GPIO§
L1D Cache
2-Way Set
Associative
4K Bytes Total


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