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SM32C6416TGLZA7EP Fiches technique(PDF) 4 Page - Texas Instruments

No de pièce SM32C6416TGLZA7EP
Description  FIXED-POINT DIGITAL SIGNAL PROCESSOR
Download  130 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

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SM32C6416T-EP
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SGUS056A − MARCH 2005 − REVISED FEBRUARY 2006
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description
The TMS320C64x
 DSPs) (including the SM32C64xT devices) are the highest-performance fixed-point DSP
generation in the TMS320C6000
 DSP platform. The TMS320C64x (C64x) device is based on the
second-generation high-performance, advanced VelociTI
 very-long-instruction-word (VLIW) architecture
(VelociTI.2
) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless
infrastructure applications. The C64x
 is a code-compatible member of the C6000 DSP platform.
With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices
offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the
operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x
DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent
functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2
extensions. The VelociTI.2
 extensions in the eight functional units include new instructions to accelerate the
performance in key applications and extend the parallelism of the VelociTI
 architecture. The C64x can produce
four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or
eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware
logic, on-chip memory, and additional on-chip peripherals similar to the other C6000
 DSP platform devices.
The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP)
and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The
VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9,
R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4,
and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock
divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations).
The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required
by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo
interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable.
Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.
The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128K-bit direct mapped cache and the Level 1 data cache (L1D) is a 128K-bit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8M-bit memory space that is
shared between program and data space. L2 memory can be configured as mapped memory or combinations
of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial
ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM)
Slave [UTOPIA Slave] port; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port
interface (HPI16/HPI32); a peripheral component interconnect (PCI); a general-purpose input/output port
(GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both
of which are capable of interfacing to synchronous and asynchronous memories and peripherals.
The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific
enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows
 debugger
interface for visibility into source code execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
† These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.


Numéro de pièce similaire - SM32C6416TGLZA7EP

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