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TCA9548APWR Fiches technique(PDF) 3 Page - Texas Instruments

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No de pièce TCA9548APWR
Description  LOW VOLTAGE 8-CHANNEL I2C SWITCH WITH RESET
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

TCA9548APWR Fiches technique(HTML) 3 Page - Texas Instruments

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TCA9548A
www.ti.com
SCPS207A – MAY 2012 – REVISED JULY 2012
TERMINAL FUNCTIONS
NO.
NAME
DESCRIPTION
TSSOP (PW)
QFN (RTW)
1
22
A0
Address input 0. Connect directly to VCC or ground.
2
23
A1
Address input 1. Connect directly to VCC or ground.
3
24
RESET
Active-low reset input. Connect to VCC through a pull-up resistor, if not used.
4
1
SD0
Serial data 0. Connect to VCC through a pull-up resistor.
5
2
SC0
Serial clock 0. Connect to VCC through a pull-up resistor.
6
3
SD1
Serial data 1. Connect to VCC through a pull-up resistor.
7
4
SC1
Serial clock 1. Connect to VCC through a pull-up resistor.
8
5
SC2
Serial data 2. Connect to VCC through a pull-up resistor.
9
6
SC2
Serial clock 2. Connect to VCC through a pull-up resistor.
10
7
SD3
Serial data 3. Connect to VCC through a pull-up resistor.
11
8
SC3
Serial clock 3. Connect to VCC through a pull-up resistor.
12
9
GND
Ground
13
10
SD4
Serial data 4. Connect to VCC through a pull-up resistor.
14
11
SC4
Serial clock 4. Connect to VCC through a pull-up resistor.
15
12
SD5
Serial data 5. Connect to VCC through a pull-up resistor.
16
13
SC5
Serial clock 5. Connect to VCC through a pull-up resistor.
17
14
SD6
Serial data 6. Connect to VCC through a pull-up resistor.
18
15
SC6
Serial clock 6. Connect to VCC through a pull-up resistor.
19
16
SD7
Serial data 7. Connect to VCC through a pull-up resistor.
20
17
SC7
Serial clock 7. Connect to VCC through a pull-up resistor.
21
18
A2
Address input 2. Connect directly to VCC or ground.
22
19
SCL
Serial clock bus. Connect to VCC through a pull-up resistor.
23
20
SDA
Serial data bus. Connect to VCC through a pull-up resistor.
24
21
VCC
Supply voltage
I
2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1). After the start condition, the device address byte
is sent, most significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (start or stop) (see Figure 2).
A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1).
Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see
Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly,
the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold
times must be met to ensure proper operation.
Copyright © 2012, Texas Instruments Incorporated
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