TCA7408

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SCPS235

– NOVEMBER 2011

Reads

The bus master first must send the TCA7408 address with the LSB set to a logic 0. The command byte is sent

after the address and determines which register is accessed.

After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register

defined by the command byte then is sent by the TCA7408.

Data is clocked into the register on the rising edge of the ACK clock pulse.

Figure 6. Read From Register

NOTE: ADDR = 0

Figure 7. Read From Input Status Register

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest

acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 0Fh

(read Input Status Register). This figure eliminates the command byte transfer, a restart, and slave address call

between the initial slave address call and actual data transfer from GPIO.

Copyright

© 2011, Texas Instruments Incorporated

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