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DAC5675AIPHP Fiches technique(PDF) 6 Page - Texas Instruments |
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DAC5675AIPHP Fiches technique(HTML) 6 Page - Texas Instruments |
6 / 26 page www.ti.com DIGITAL SPECIFICATIONS DAC5675A SBAS334C – NOVEMBER 2004 – REVISED MARCH 2005 Over operating free-air temperature range. Typical values at +25°C, AV DD = 3.3V, DVDD = 3.3V, unless otherwise noted. DAC5675A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS Interface: nodes D[13:0]A, D[13:0]B VITH+ Positive-going differential input voltage 100 mV threshold See LVDS min/max threshold voltages table VITH- Negative-going differential input voltage -100 mV threshold ZT Internal termination impedance 90 110 132 Ω CI Input capacitance 2 pF CMOS Interface (SLEEP): VIH High-level input voltage 2 3.3 V VIL Low-level input voltage 0 0.8 V IIH High-level input current –100 100 µA IIL Low-level input current –10 10 µA Input capacitance 2 pF Clock Interface (CLK, CLKC): |CLK- Clock differential input voltage 0.4 0.8 VPP CLKC| Clock duty cycle 40 60 % VCM Common-mode voltage range 2 ±20% V Input resistance Node CLK, CLKC 670 Ω Input capacitance Node CLK, CLKC 2 pF Input resistance Differential 1.3 k Ω Input capacitance Differential 1 pF Timing tSU Input setup time 1.5 ns tH Input hold time 0 ns tDD Digital delay time (DAC latency) 3 clk 6 |
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