CDCS503TPWRQ1 datasheet(6/14 Pages) TI1

No de pièce	CDCS503TPWRQ1

Description	Clock Buffer/Clock Multiplier With Optional SSC

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Fabricant	TI1 [Texas Instruments]

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VDD

1 kW

CDCS503-Q1

LVCMOS

1 kW

10 pF

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f -InputFrequency-MHz

i

x1Mode

x4Mode

CDCS503-Q1

SCAS924B – MARCH 2012 – REVISED JUNE 2012

www.ti.com

Figure 2. IDD vs Input Frequency, VCC = 3.3 V, SSC = 2%,

Output Loaded With Test Load

APPLICATION INFORMATION

SSC MODULATION

The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS503-Q1

device uses a triangular modulation scheme implemented in a way that the modulation frequency depends on

the VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency.

The modulation frequency can be calculated by using one of the below formulas chosen by frequency

multiplication mode.

FS = 0: fmod = fIN / 708

FS = 1: fmod = fIN / 620

PARAMETER MEASUREMENT INFORMATION

Figure 3. Test Load

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