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CDCLVP2106RHAT Fiches technique(PDF) 9 Page - Texas Instruments |
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CDCLVP2106RHAT Fiches technique(HTML) 9 Page - Texas Instruments |
9 / 23 page V IL V IH V th V th IN IN V IHmax V ILmax V IHmin V ILmin V IH V IL V th V th V thmax V thmin GND V CC LVPECL V CC V CC 130 W 82 W 130 W 82 W CDCLVP2106 CDCLVP2106 www.ti.com SCAS887A – SEPTEMBER 2009 – REVISED AUGUST 2011 TEST CONFIGURATIONS This section describes the function of each block for the CDCLVP2106. Figure 3 through Figure 9 illustrate how the device should be setup for a variety of test configurations. Figure 3. DC-Coupled LVCMOS Input During Device Test Figure 4. Vth Variation over LVCMOS Levels Figure 5. DC-Coupled LVPECL Input During Device Test Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): CDCLVP2106 |
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