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CDCLVD1213RGTR Fiches technique(PDF) 9 Page - Texas Instruments

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No de pièce CDCLVD1213RGTR
Description  1:4 Low Additive Jitter LVDS Buffer With Divider
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

CDCLVD1213RGTR Fiches technique(HTML) 9 Page - Texas Instruments

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FerriteBead
1 µF
10 µF
0.1 µF
LVDS
Z = 50 W
CDCLVD1213
100 W
Z = 50 W
LVDS
Z = 50 W
CDCLVD1213
100 W
Z = 50 W
100 nF
100 nF
CDCLVD1213
www.ti.com
SCAS897 – JULY 2010
POWER-SUPPLY FILTERING
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against
the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the
device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they
must be placed close to the power-supply pins and laid out with short loops to minimize inductance. It is
recommended to add as many high-frequency (for example, 0.1 µF) bypass capacitors as there are supply pins
in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and
the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip
supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for
proper operation.
Figure 12. Power-Supply Decoupling
LVDS OUTPUT TERMINATION
The proper LVDS termination for signal integrity over two 50
Ω lines is 100 Ω between the outputs on the
receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is
recommended to place termination resister close to the receiver. If the receiver is internally biased, ac-coupling
should be used. If the LVDS receiver has internal 100
Ω termination, external termination is not required.
Unused outputs can be left open without connecting any traces to the output pins.
Figure 13. Output DC Termination
Figure 14. Output AC Termination (With Receiver Internally Biased)
Copyright © 2010, Texas Instruments Incorporated
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