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CDCEL913-Q1 Fiches technique(PDF) 7 Page - Texas Instruments |
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CDCEL913-Q1 Fiches technique(HTML) 7 Page - Texas Instruments |
7 / 26 page CDCEL913-Q1 www.ti.com SCAS888 – SEPTEMBER 2009 DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT OVERALL PARAMETER All outputs off, fCLK = 27 MHz, All PLLS on 11 IDD Supply current (see Figure 3) fVCO = 135 MHz; mA 9 Per PLL fOUT = 27 MHz VDDOUT = 3.3 V 1.3 No load, all outputs on, IDD(OUT) Supply current (see Figure 4 and Figure 5) mA fOUT = 27 MHz VDDOUT = 1.8 V 0.7 Power-down current. Every circuit powered IDD(PD) fIN = 0 MHz, VDD = 1.9 V 30 μA down except SDA/SCL Supply voltage Vdd threshold for power-up V(PUC) 0.85 1.45 V control circuit fVCO VCO frequency range of PLL 80 230 MHz VDDOUT = 3.3 V 230 fOUT LVCMOS output frequency MHz VDDOUT = 1.8 V 230 LVCMOS PARAMETER VIK LVCMOS input voltage VDD = 1.7 V; II = –18 mA –1.2 V II LVCMOS Input current VI = 0 V or VDD; VDD = 1.9 V ±5 μA IIH LVCMOS Input current for S0/S1/S2 VI = VDD; VDD = 1.9 V 5 μA IIL LVCMOS Input current for S0/S1/S2 VI = 0 V; VDD = 1.9 V –4 μA Input capacitance at Xin/Clk VIClk = 0 V or VDD 6 CI Input capacitance at Xout VIXout = 0 V or VDD 2 pF Input capacitance at S0/S1/S2 VIS = 0 V or VDD 3 CDCE913 - LVCMOS PARAMETER FOR VDDOUT = 3.3 V – MODE VDDOUT = 3 V, IOH = –0.1 mA 2.9 VOH LVCMOS high-level output voltage VDDOUT = 3 V, IOH = –8 mA 2.4 V VDDOUT = 3 V, IOH = –12 mA 2.2 VDDOUT = 3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 3 V, IOL = 8 mA 0.5 V VDDOUT = 3 V, IOL = 12 mA 0.8 tPLH, tPHL Propagation delay PLL bypass 3.2 ns tr/tf Rise and fall time VDDOUT = 3.3 V (20%–80%) 0.6 ns tjit(cc) Cycle-to-cycle jitter(2) (3) 1 PLL switching, Y2-to-Y3 50 70 ps tjit(per) Peak-to-peak period jitter(3) 1 PLL switching, Y2-to-Y3 60 100 ps tsk(o) Output skew (4) , See Table 2 fOUT = 50 MHz; Y1-to-Y3 60 ps odc Output duty cycle (5) fVCO = 100 MHz; Pdiv = 1 45% 55% CDCE913 – LVCMOS PARAMETER for VDDOUT = 2.5 V – Mode VDDOUT = 2.3 V, IOH = –0.1 mA 2.2 VOH LVCMOS high-level output voltage VDDOUT = 2.3 V, IOH = –6 mA 1.7 V VDDOUT = 2.3 V, IOH = –10 mA 1.6 VDDOUT = 2.3 V, IOL = 0.1 mA 0.1 VOL LVCMOS low-level output voltage VDDOUT = 2.3 V, IOL = 6 mA 0.5 V VDDOUT = 2.3 V, IOL = 10 mA 0.7 tPLH, tPHL Propagation delay PLL bypass 3.6 ns tr/tf Rise and fall time VDDOUT = 2.5 V (20%–80%) 0.8 ns tjit(cc) Cycle-to-cycle jitter(2) (3) 1 PLL switching, Y2-to-Y3 50 70 ps tjit(per) Peak-to-peak period jitter(3) 1 PLL switching, Y2-to-Y3 60 100 ps tsk(o) Output skew(4) , See Table 2 fOUT = 50 MHz; Y1-to-Y3 60 ps odc Output duty cycle(5) fVCO = 100 MHz; Pdiv = 1 45% 55% (1) All typical values are at respective nominal VDD. (2) 10000 cycles. (3) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, fVCO = 108 MHz, fOUT = 27 MHz (measured at Y2). (4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider. (5) odc depends on output rise and fall time (tr/tf); data sampled on rising edge (tr) Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): CDCEL913-Q1 |
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