Moteur de recherche de fiches techniques de composants électroniques
Selected language     French  ▼
Nom de la pièce
         Description


74ACT11867 Datasheet(Fiches technique) 6 Page - Texas Instruments

Numéro de pièce 74ACT11867
Description  SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR
Télécharger  11 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo 

 6 page
background image
74ACT11867
SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER
WITH ASYNCHRONOUS CLEAR
SCAS178A − DECEMBER 1991 − REVISED FEBRUARY 1998
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C
MIN
MAX
UNIT
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
MIN
MAX
UNIT
I
50 A
4.5 V
4.4
4.4
IOH = −50 μA
5.5 V
5.4
5.4
VOH
IOH = −24 mA
4.5 V
3.94
3.8
V
VOH
IOH = −24 mA
5.5 V
4.94
4.8
V
IOH = −75 mA
5.5 V
3.85
I
50 A
4.5 V
0.1
0.1
IOL = 50 μA
5.5 V
0.1
0.1
VOL
I
24 mA
4.5 V
0.36
0.44
V
VOL
IOL = 24 mA
5.5 V
0.36
0.44
V
IOL = 75 mA
5.5 V
1.65
II
VI = VCC or GND
5.5 V
±0.1
±1
μA
ICC
VI = VCC or GND,
IO = 0
5.5 V
8
80
μA
ΔICC‡
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
0.9
1
mA
Ci
VI = VCC or GND
5 V
4.5
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range, VCC = 5 V
± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
70
0
70
MHz
t
Pulse duration
S0 and S1 low
12
12
ns
tw
Pulse duration
CLK
6.5
6.5
ns
Data
8
8
ENP, ENT
4
4
tsu§
Setup time before CLK
S0, S1 (load)
11
11
ns
tsu
Setup time before CLK
S0, S1 (count down)
11
11
ns
S0, S1 (count up)
11
11
th
Hold time after CLK
Data
1
1
ns
tskew
Skew time between S0 and S1 to avoid inadvertent clear
S0 and S1 low
0
0
ns
§ This setup time is required to ensure stable data.
This is the maximum time for which S0 and S1 can be low simultaneously when the device transitions between the load (S1 = H, S0 = L) and
count-down (S1 = L, S0 = H) modes.




Html Pages

1  2  3  4  5  6  7  8  9  10  11 


Datasheet Download




Lien URL

AllDATASHEET vous a-t-il été utile ?   [ DONATE ]  

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Favoris   |   Echange de liens   |   Fabricants
All Rights Reserved © Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl