AD7457_05 datasheet(7/20 Pages) AD

No de pièce	AD7457

Description	Low Power, Pseudo Differential, 100 kSPS

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AD7457

Rev. A | Page 7 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD7457

TOP VIEW

(Not to Scale)

VDD 1

SCLK

2

SDATA

3

CS

4

VREF

VIN+

VIN–

GND

8

7

6

5

Figure 4. 8-Lead SOT-23 Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VDD

Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 µF capacitor and a

10 µF tantalum capacitor.

2

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also

used as the clock source for the conversion process.

3

SDATA

Serial Data. Logic output. The conversion result from the AD7457 is provided on this output as a serial data

stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7457 consists of

four leading zeros followed by the 12 bits of conversion data that are provided MSB first. The output coding is

straight (natural) binary.

4

CS

Chip Select. This input provides the dual function of powering up the device and initiating a conversion on the

AD7457.

5

GND

Analog Ground. Ground reference point for all circuitry on the AD7457. All analog input signals and any external

reference signal should be referred to this GND voltage.

6

VIN–

Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc offset to

provide a pseudo ground.

7

VIN+

Noninverting Analog Input.

8

VREF

Reference Input for the AD7457. An external reference in the range 100 mV to VDD must be applied to this input.

The specified reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.33 µF.

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