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ADV7533 Fiches technique(PDF) 10 Page - Analog Devices |
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ADV7533 Fiches technique(HTML) 10 Page - Analog Devices |
10 / 12 page ADV7533 Rev. 0 | Page 10 of 12 Pin No. Mnemonic Type1 Description G7 A2VDD P 1.8 V Power Supply for MIPI/DPHY Input. Should be filtered and as quiet as possible. E2, E4, G1 DVDD P 1.8 V Power Supply for Digital and I/O Power Supply. Supply power to the digital logic and I/Os. Should be filtered and as quiet as possible. C6 PVDD P 1.8 V Power Supply for the PLL. Should be filtered and as quiet as possible. This supply is the most noise sensitive. B1 V3P3 P 3.3 V programming pin for HDCP nonvolatile memory. B2, B3, B5, B6, C7, E1, E7, F1, F7 GND P Ground for all domains. E5 SDA C Serial Port Data I/O. Serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. E6 SCL C Serial Port Data Clock. Serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. D2 DDCSDA C Serial Port Data I/O to Receiver. Serves as the master to the DDC bus. 5 V CMOS logic level. D1 DDCSCL C Serial Port Data Clock to Receiver. Serves as the master clock for the DDC bus. 5 V CMOS logic level. D6 CEC I/O CEC I/O. If unused, pin should be connected to ground. D7 CEC_CLK I CEC External Clock. Can be from 3 MHz to 100 MHz. Settings default to 12 MHz. If unused, pin should be connected to ground. 1 I = input, O = output, P = power supply, C = control. |
Numéro de pièce similaire - ADV7533 |
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Description similaire - ADV7533 |
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