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ADV7533 Fiches technique(PDF) 5 Page - Analog Devices |
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ADV7533 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 12 page ADV7533 Rev. 0 | Page 5 of 12 ADV7533BCBZ Parameter Conditions Temp Test Level1 Min Typ Max Unit AVDD HDMI analog core (24 bits at 720p) Full IV 11 mA V1P2 (1.2 V) HDMI/DSI digital core (DSI 30 bits/HDMI 24 bits at 720p) Full IV 39 mA A2VDD MIPI DPHY (30 bits/three lanes/720p) Full IV 12 mA PVDD HDMI PLL (24 bits at 720p) Full IV 11 mA V3P3—HDMI/HDCP Memory HDMI HDCP memory Full IV 0.3 mA Transmitter Total Power 720p, 30-bit DSI in; 720p, 36-bit HDMI out; typical random pattern with CSC enabled, HDCP enabled, audio enabled V1P2 = 1.2 V Full IV 120 154 mW V1P2 = 1.8 V Full VI 204 mW AC SPECIFICATIONS TMDS Output Clock Frequency 25°C IV 20 112 MHz TMDS Output Clock Duty Cycle 25°C IV 48 52 % TMDS Differential Swing 25°C VII 800 1000 1200 mV Differential Output Timing Low-to-High Transition Time 25°C VII 75 175 ps High-to-Low Transition Time 25°C VII 75 175 ps AUDIO AC TIMING2 SCLK Duty Cycle When N = Even Number Full IV 40 50 60 % When N = Odd Number Full IV 49 50 51 % I2S, S/PDIF Setup, tASU Full IV 2 ns I2S, S/PDIF Hold Time, tAHLD Full IV 2 ns LRCLK Setup Time, tASU Full IV 2 ns LRCLK Hold Time, tAHLD Full IV 2 ns CEC CEC_CLK Frequency3 Full VIII 3 12 100 MHz CEC_CLK Accuracy Full VIII −2 +2 % CEC_CLK Duty Cycle Full VIII 40 60 % I2C INTERFACE SCL Clock Frequency Full VIII 4004 kHz SDA Setup Time, tDSU Full VIII 100 ns SDA Hold Time, tDHO Full VIII 100 ns Setup for Start, tSTASU Full VIII 0.6 μs Hold Time for Start, tSTAH Full VIII 0.6 μs Setup for Stop, tSTOSU Full VIII 0.6 μs Bus Free Between Stop and Start, tBUF Full VIII 1.3 μs SCL High, tHIGH Full VIII 0.6 μs SCL Low, tLOW Full VIII 1.3 μs 1 See the section. Explanation of Test Levels 2 12 MHz crystal for default register settings. 3 Only applies to S/PDIF if external MCLK is used. 4 I2C data rates of 100 KHz and 400 KHz are supported. |
Numéro de pièce similaire - ADV7533 |
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Description similaire - ADV7533 |
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