 |
Moteur de recherche de fiches techniques de composants électroniques |
|
|
Moteur de recherche de fiches techniques de composants électroniques |
|
AD9253BCPZRL7-105 Fiches technique(PDF) 6 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD9253BCPZRL7-105 Fiches technique(HTML) 6 Page - Analog Devices |
|
|
6 / 40 page  AD9253 Data Sheet Rev. 0 | Page 6 of 40 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. Parameter1, 2 Temp Min Typ Max Unit CLOCK3 Input Clock Rate Full 10 1000 MHz Conversion Rate Full 10 80/105/125 MSPS Clock Pulse Width High (tEH) Full 6.25/4.76/4.00 ns Clock Pulse Width Low (tEL) Full 6.25/4.76/4.00 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 2.3 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/16) ns DCO to Data Delay (tDATA)4 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/16) − 300 (tSAMPLE/16) (tSAMPLE/16) + 300 ps Lane Delay (tLD) 90 ps Data to Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 250 ns Wake-Up Time (Power-Down)5 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter, tJ) 25°C 135 fs rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode. TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS See Figure 74 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 74) 10 ns min tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 74) 10 ns min |
Numéro de pièce similaire - AD9253BCPZRL7-105 |
|
Description similaire - AD9253BCPZRL7-105 |
|
|
Lien URL |
| Politique de confidentialité |
| ALLDATASHEET.FR |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
French ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
