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CD-700-SYNCE-25M0000000 Datasheet(Fiches technique) 4 Page - Vectron International, Inc
Numéro de pièce
VECTRON [Vectron International, Inc]
CD-700-SYNCE-25M0000000 Datasheet(HTML) 4 Page - Vectron International, Inc
/ 11 page
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Page 4 of 11
CD-700 Theory of Operation
The phase detector has two buffered inputs (DATAIN and CLKIN) which are designed to switch at 1.4 volts. DATAIN is designed to
accept an NRZ data stream but may also be used for clock signals which have a 50% duty cycle. CLKIN is connected to OUT1 or
OUT2, or a divided version of one of these outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the
power supply voltage or ground by more than a few hundred millivolts.
The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to produce a DC signal
proportional to the phase between the CLKIN and DATAIN signals (see Figure 4 for a block diagram and Figure 5 for an open loop
transfer curve). This will simplify the PLL design as the designer does not have to filter narrow pulse signals to a DC level. Under
locked conditions the rising edge of CLKIN will be centered in the middle of the DATAIN signal (see Figure 6).
Figure 4. Simplified Phase Detector Block Diagram
The phase detector gain is 0.53V/rad x data density for 5volt
operation and 0.35V/rad x data density for 3.3 volt opera-
tion. Data density is equal to 1.0 for clock signals and is
system dependent on coding and design for NRZ signals,
but 0.25 could be used as a starting point for data density.
The phase detector output is a DC signal for DATAIN fre-
quencies greater than 1 MHz but produces significant ripple
when inputs are less than 200 kHz. Additional filtering is
required for lower input frequencies applications such as
8kHz (see Figures 8 and 9 as examples).
Under closed loop conditions the active filter has a block-
ing capacitor which provides a very high DC gain, so under
normal locked conditions and input frequencies >1 MHz, PHO will be about VDD/2 and will not vary significantly with changes in
input frequency (within lock range). The control voltage (pin 16) will vary according to the input frequency offset, but PHO will
remain relatively constant.
Figure 5. Open Loop Phase Detecto Transfer Curve
Recovered Clock and Data Alignment
The CD-700 is designed to recover an embedded clock from
an NRZ data signal and retime it with a data pattern. In this
application, the VCXO frequency is exactly the same frequency
as the NRZ data rate and the outputs are taken off Pin 9 (RCLK),
and Pin 10 (RDATA). Under locked conditions, the falling edge of
RCLK is centered in the RDATA pattern. Also, there is a 1.5 clock
cycle delay between DATAIN and RDATA. Figure 6 shows the
relationship between the DATAIN, CLKIN, RDATA and RCLK.
Figure 6. Clock and Data Timing Relationships for the NRZ data
Other RZ encoding schemes such as Manchester or AMI can be accomodated by using a CD-700 at twice the baud rate.
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