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AD5110 Fiches technique(PDF) 9 Page - Analog Devices |
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AD5110 Fiches technique(HTML) 9 Page - Analog Devices |
9 / 24 page Data Sheet AD5111/AD5113/AD5115 Rev. 0 | Page 9 of 24 INTERFACE TIMING SPECIFICATIONS VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter Test Conditions/Comments Min Typ Max Unit Description fCLK VDD ≥ 2.7 V 50 MHz Clock frequency VDD < 2.7 V 25 MHz t1 25 ns CS setup time t2 VDD ≥ 2.7 V 10 ns CLK low time VDD < 2.7 V 20 ns t3 VDD ≥ 2.7 V 10 ns CLK high time VDD < 2.7 V 20 ns t4 15 ns U/D setup time t5 6 ns U/D hold time t6 VDD ≥ 2.7 V 20 ns CS rise to CLK hold time VDD < 2.7 V 40 ns t7 15 ns CS rising edge to next CLK ignored t8 VDD ≥ 2.7 V 12 ns U/D minimum pulse time VDD < 2.7 V 24 ns t9 12 ns U/D rise to CLK falling edge t10 1 µs Minimum CS time tEEPROM_PROGRAM1 15 50 ms Memory program time tPOWER_UP2 50 µs Power-on EEPROM restore time 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. 2 Maximum time after VDD is equal to 2.3 V. TIMING DIAGRAMS t1 RWB CLK CS U/D t2 t4 t5 t6 t3 t10 t7 Figure 2. Increment/Decrement Mode Timing DATA EEPROM NEW DATA tEEPROM_PROGRAM t1 CLK CS U/D t8 t6 Figure 3. Storage Mode Timing CS CLK U/D t1 t9 t6 Figure 4. Shutdown Mode Timing |
Numéro de pièce similaire - AD5110 |
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Description similaire - AD5110 |
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