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9DB102BFILFT Fiches technique(PDF) 2 Page - Integrated Device Technology |
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9DB102BFILFT Fiches technique(HTML) 2 Page - Integrated Device Technology |
2 / 13 page IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 852 REV K 04/01/10 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 2 Pin Configuration PLL_BW 1 20 VDDA CLK_INT 2 19 GNDA CLK_INC 3 18 IREF **CLKREQ0# 4 17 **CLKREQ1# VDD 5 16 VDD GND 6 15 GND PCIEXT0 7 14 PCIEXT1 PCIEXC0 8 13 PCIEXC1 VDD 9 12 VDD SMBDAT 10 11 SMBCLK Note: Pins preceeded by '**' have internal 120K ohm pull down resistors 20-pin SSOP & TSSOP VDD GND 5,9,12,16 6,15 PCI Express Outputs 9 6 SMBUS 20 19 IREF 20 19 Analog VDD & GND for PLL core Description Pin Number Power Groups Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 PLL_BW INPUT 3.3V input for selecting PLL Band Width 0 = low, 1= high 2 CLK_INT INPUT "True" reference clock input. 3 CLK_INC INPUT "Complementary" reference clock input. 4 **CLKREQ0# INPUT Output enable for SRC/PCI Express output pair '0' 0 = enabled, 1 = tri-stated 5 VDD POWER Power supply, nominal 3.3V 6 GND POWER Ground pin. 7 PCIEXT0 OUTPUT True clock of differential PCI_Express pair. 8 PCIEXC0 OUTPUT Complement clock of differential PCI_Express pair. 9 VDD POWER Power supply, nominal 3.3V 10 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant 11 SMBCLK INPUT Clock pin of SMBUS circuitry, 5V tolerant 12 VDD POWER Power supply, nominal 3.3V 13 PCIEXC1 OUTPUT Complement clock of differential PCI_Express pair. 14 PCIEXT1 OUTPUT True clock of differential PCI_Express pair. 15 GND POWER Ground pin. 16 VDD POWER Power supply, nominal 3.3V 17 **CLKREQ1# INPUT Output enable for SRC/PCI Express output pair '1' 0 = enabled, 1 = tri-stated 18 IREF OUTPUT This pin establishes the reference current for the differential current- mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 19 GNDA POWER Ground pin for the PLL core. 20 VDDA POWER 3.3V power for the PLL core. Pins preceeded by '**' have internal 120K ohm pull down resistors Note: |
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