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DAC1405D750 Fiches technique(PDF) 1 Page - NXP Semiconductors

No de pièce DAC1405D750
Description  Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

DAC1405D750 Fiches technique(HTML) 1 Page - NXP Semiconductors

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1.
General description
The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 4
 or 8 interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q
inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a
Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and
the phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
A 4
 and 8 clock multiplier enables the DAC1405D750 to provide the appropriate
internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use
of an external high frequency clock. The voltage regulator enables adjustment of the
output full-scale current.
2.
Features and benefits
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating
Rev. 4 — 7 June 2011
Product data sheet
Dual 14-bit resolution
IMD3: 74 dBc; fs = 737.28 Msps;
fo = 140 MHz
750 Msps maximum update rate
ACPR: 72 dBc; 2-carrier WCDMA;
fs = 737.28 Msps; fo =153.6 MHz
Selectable 4
 or 8 interpolation filters Typical 1.2 W power dissipation at 4
interpolation, PLL off and 740 Msps
Input data rate up to 185 Msps
Power-down and Sleep modes
Very low noise cap-free integrated PLL Differential scalable output current from
1.6 mA to 22 mA
32-bit programmable NCO frequency
On-chip 1.25 V reference
Dual port or Interleaved data modes
External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
Internal digital offset control
LVDS compatible clock
Inverse x / (sin x) function
Two’s complement or binary offset
data format
Fully compatible SPI port
1.8 V/3.3 V CMOS input data buffers
Industrial temperature range from
40 C to +85 C


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