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FM28V020-SGTR Fiches technique(PDF) 2 Page - Ramtron International Corporation

No de pièce FM28V020-SGTR
Description  256Kbit Bytewide F-RAM Memory
Download  14 Pages
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Fabricant  RAMTRON [Ramtron International Corporation]
Site Internet  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM28V020-SGTR Fiches technique(HTML) 2 Page - Ramtron International Corporation

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FM28V020 - 32Kx8 F-RAM
Rev. 2.1
June 2011
Page 2 of 14
Figure 1. Block Diagram
Pin Descriptions
Pin Name
Type
Pin Description
A(14:0)
Input
Address inputs: The 15 address lines select one of 32,768 bytes in the F-RAM array. The
address value is latched on the falling edge of /CE. Addresses A(2:0) are used for page
mode read and write operations.
/CE
Input
Chip Enable input: The device is selected and a new memory access begins on the falling
edge of /CE. The entire address is latched internally at this point.
/WE
Input
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM28V020 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE
latches a new column address for fast page mode write cycles.
/OE
Input
Output Enable: When /OE is low, the FM28V020 drives the data bus when valid data is
available. Deasserting /OE high tri-states the DQ pins.
DQ(7:0)
I/O
Data: 8-bit bi-directional data bus for accessing the F-RAM array.
VDD
Supply
Supply Voltage
VSS
Supply
Ground
Control
Logic
WE
A(14:3)
A(2:0)
I/O Latch & Bus Driver
OE
DQ(7:0)
4K x 64
F-RAM Array
A(14:0)
Column Decoder
. . .
CE


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