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TPS54320RHLR Fiches technique(PDF) 11 Page - Texas Instruments |
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TPS54320RHLR Fiches technique(HTML) 11 Page - Texas Instruments |
11 / 39 page Vout Vref R8 R9 Vref - = TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 34, start with a 10 k Ω resistor for R9 and use Equation 1 to calculate R8. To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable. (1) Where Vref = 0.8V The minimum output voltage and maximum output voltage can be limited by the minimum on time of the high-side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation. Safe Start-up into Pre-Biased Outputs The device has been designed to prevent the low-side MOSFET from discharging a prebiased output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to turn on until the SS/TR pin voltage is higher than the VSENSE pin voltage. Error Amplifier The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The transconductance of the error amplifier is 1300 mA/V during normal operation. The frequency compensation network is connected between the COMP pin and ground. Slope Compensation The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range. Enable and Adjusting Under-Voltage Lockout The EN pin provides an electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low Iq state. The EN pin has an internal pull-up current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use an open drain or open collector output logic to interface with the pin. The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150mV. If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN pin, in split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18 or Figure 19. When using the external UVLO function, it is recommended to set the hysteresis to be greater than 500mV. The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2 and Equation 3. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s) :TPS54320 |
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